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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: pgerassi who wrote (254140)	7/17/2008 1:31:47 AM
From: eracer	Read Replies (1) \| Respond to of 275872

Re: Lets first take your obviously biased statement that a 2nd gen 45nm SOI R810 like core, 80:4:4:64:16, (shaders:TFUs:ROPs:memory bits:PCIe lanes) could be just 20mm2. Obviously you don't know about QAD back of the envelope calculations. Lets look at the details leading to this. First any core on Fusion would be sans ODMC, PCIe and any interface (it goes down the existing HT, ODMC and additional NB ones for PCIe which will be outside the core area). Thus the last two numbers above are missing. These tend to be large areas. You can easily see that looking at any Opteron, Athlon64 or Turion dies, especially Barcelona from which Shrike will use Shanghai as a basis. ... Trying it nets only that x4 is 39.67mm2. Given that the R620 core on 55nm bulk is 27.33mm2 including the PCIe interface not in the core above. Given that 45nm/55nm squared is ideal scaling, the highest scale factor would be 0.67... In your calculations you pretend that anything in a GPU that isn't shaders, texture units, ROPs, or PCIe lanes must be the memory interface. What about UVD? Does that magically take up 0 mm^2 of die space and no transistors? Using your estimate that a 55-nm 64-bit memory inteface requires 39.67 mm^2, then a 55-nm 128-bit interface uses 79.34 mm^2. Given perfect scaling (since you seem to believe in it) from 65-nm to 55-nm we find that a 65-nm 128-bit memory interface would require 111 mm^2. Brisbane is 126mm^2. Congratulations! You just proved both Brisbane dies take a total of 15mm^2 while the memory controller takes up the other 111mm^2! So much for back of the envelope calculations.