Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: eracer who wrote (254141)	7/17/2008 12:50:50 PM
From: pgerassi	Read Replies (1) \| Respond to of 275872

Eracer: Most of memory interface does not scale much, if at all since higher currents (memory interfaces get faster over time) have to be supplied and at higher voltages than the core logic. Thus these eat up any gains in current density. The memory thus is likely to be almost the same size whether its 90nm, 65nm, 55nm or 45nm. The actual memory control logic is likely very small at 55nm, about 1mm2. All this is obvious if you look at die layouts at the various sizes. This also includes PCIe interfaces and that uses in crossfire which are not in that x4 estimate. So the estimate for x1, x2, x3 and a part of x5 which comprise the core are likely to be even smaller than the estimate. You also can't really use the x4 estimate for the ones on the CPU because GPU frame buffer memory is usually faster than main memory used in PCs. Thus it needs more current and thus more die area than a similar CPU version especially since the latter uses a more high performance process. AMD's 65nm SOI yields more current density than TSMC's 55nm bulk logic. The former is optimized for speed while the latter is optimized for yield. Besides, to get a decent estimate for the other areas, we need a 5th die design at 55nm. And to put reasonable bounds on them, a 6th would be needed as we would get 6 different estimates of each gotten by excluding one of the six for each calculation. Then you generally figure a central point for each and thus tighten the estimate for a different combo as you can use well known scaling factors for each kind of use. Of course all this leads to a QAD estimate. Quick because it ignores certain things and dirty because of such things as dead areas, optimization, feature creep and different amounts of metal layers that throw them off. Like anything else, the more details you account for, the higher the quality of the resulting estimate. Case in point would be if you combined x3 and x5 (y3) plus combining x2 and x4 (y2) and use just the three R600 designs. You get y1 as -12, y2 as 107 and y3 as -24. Clearly wrong. It comes about because the ROPs quadrupled on the R670 over the RV620 and RV635 throwing the numbers way off. Clearly one must use some sense to whittle incorrect answers away. Thus your answers are whittled away due to glaring holes in your knowledge or purposely using poor assumptions to ridicule a method with some utility. They say, assumptions are the mother of all royal foulups (the nastier terms typically used are not allowed on this board). I see that you seem to do it a lot. Pete