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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Petz who wrote (25538)	11/5/1997 11:33:00 PM
From: Bill Jackson	Respond to of 1578588

Petz. I get you. I thought that AMD was trying a workaround for Slot 1 that was capable of allowing it to operate on the same motherboard with a ZIF as I commented. Bill

To: Petz who wrote (25538)	11/5/1997 11:43:00 PM
From: Elmer	Read Replies (1) \| Respond to of 1578588

Petz, if you are saying that Intel plans to use the Alpha Bus protocal for Merced, may I ask for a source for this claim? EP

To: Petz who wrote (25538)	11/6/1997 1:40:00 AM
From: Brian Hutcheson	Respond to of 1578588

Petz , interesting socket 7 backside bus article ... In November Byte mag page 73 . It contains 3 possible configurations 1. a daughter board plugging from CPU into Mboard with an above 100 mhz bus connecting cache controller and L2 cache. 2 a daughter board that plugs into the bus between the cpu and cache and controller , this bus runs at 66/100 mhz. 3. a multichip module complete with internal cache a la Pentium Pro This also plugs into socket 7 . They feel that the external bus speed would hold back socket 7 , however until much faster Dram is being produced these very fast external busses will buy nothing . Also by the time memory speed increases , other busses like Rambus Dram may make these slot 1 / 2 academic . Brian