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Technology Stocks : Dell Technologies Inc. -- Ignore unavailable to you. Want to Upgrade?

To: Paul Merriwether who wrote (22012)	11/18/1997 8:37:00 PM
From: Meathead	Read Replies (1) \| Respond to of 176387

Paul - Todays motherboards are pushing the limits of physics. Routing and interconnects are extremely challanging. Try performing a pin escape on a 500pin BGA with 15mil ball edge spacing. Minimum stackup for any serious quality motherboard is 6 layers with tight impedance controls, many are 8 to 10 layers. Only the very cheap, marginally stable 66mhz motherboards with low component densities can be routed on 4 layers. Pads is a toy. Allegro with Specctra is more of an industry standard today for layout. There are only a handful of good signal integrity simulation tools and they require highly skilled individuals to run them, develop models, scripts, run permutations and identify the solution space for each technology. Electrical, timing and signal purity specifications must be translated into the physical geometric design rules for CAD. On top of that, these tools cost between 40k and 80k per license! Consider 100mhz busses using copper and FR4. Not easy. Look at the PC100 sdram spec from Intel that Dell helped develop. Allowable clock skews of less than 200 picoseconds across multiple PCB's. Flight times of less than 3 nanoseconds for memory data distributed across multiple DIMM loads equaling 60pf. Address lines with 250pf. Edge rates around 150ps. Potential for prototypes being dead in the water is very high unless you simulate everything. It didn't use to be this way. Theres the 100mhz GTL bus with it's open drain buffers and 1.5v swings. There's AGP with it's data strobe matching requirements in the picoseconds again. The list goes on. I've been developing PC motherboards for just over 10 years and they are far more challanging today than just 2 years ago. It's becoming more like VLSI chip design on a physical/macro level. In fact, the tools motherboard designers use are almost identical. Here's a primer on the subject by interconnectix if you are so inclined.. 192.94.39.7 Unfortunately, we evaluated their tool and it was a flop. They are improving however. I will beat anyone over the head relentlessly with this stuff until they realize designing a dense, state of the art motherboard is no etch-a-sketch connect the dots endeavour. It's getting harder everyday and those smaller companies who don't have the experience or resources like Dell and Compaq aren't going to survive. MEATHEAD

To: Paul Merriwether who wrote (22012)	11/18/1997 11:07:00 PM
From: Meathead	Respond to of 176387

Oh yeah... and re: "I was not impressed with PC manufacturers' technology then and I find it hard to believe that they have suddenly leapfrogged and are leading technology" They are not leading technology in every area but pushing the envelope in some. They have leapfrogged your stale grad school concepts however. "consider the challenges faced by a VLSI designer who has to connect hundreds of thousands + transistors. And repeat it thousands of times as development progresses. And then do it for different vendors libraris. And then verify that the timing passes for all temperatures in the ragnge. THAT, my friend, is non-trivial. Just to give you a sense of scale, th echip I last worked on had more than 400 pins, mixed signals and 6 major modules. The timing was a lot tighter than you as a board level designer can EVER imagine(and the timing analysis tools a lot more complex than you can ever need for pcb's)." This is what PCB designers are facing today. The timing tools are nearly identical. Timing budgets AS A PERCENTAGE OF CYCLE TIME for copper and FR4 are every bit as complex to deal with as timing budgets for metal and silicon. Consider runing multiple simulations across temprature, process and voltage of all I/O cells for the purpose of qualifying numerous memory vendors. Within temp and process, vary tline lengths, impedances, spacing, odd/even coupling modes, connector parasitics. Then consider loading permutations. Proper simulation just one data line to find electrical breaking points require thousands of simulations. There are thousands of traces on a motherboard as well. IC design does not craft every one of the hundreds of thousands of cells by hand, ever heard of cut and paste? Furthermore, ASIC design is far more symmetrical from a layout standpoint, somthing MB design is not. You chip designer guys are all alike. So superior. You think it's so-much-more-difficult to design an ASIC when it's really the same as system integration in a tinier scale. Motherboards are big MCM's. Ask Intel how simple they think it is to do MB design these days. I watch them struggle regularly. MEATHEAD