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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Maxwell who wrote (26286)	12/1/1997 1:23:00 AM
From: Tiley	Read Replies (1) \| Respond to of 1572776

Maxwell, Re" Processor Improvements", All the factors you've stated are correct but ask yourself this question: "For a given Instruction Set Architecture, in this case the x86, where have the maximum gains in performance come from as we've gone from generation to generation ?". I can tell this for sure, those who continue to insist on CPU architecture as the answer have never designed a processor before and are armchair quarterbacking. The ideal design is one where the chip architecture and logic partitioning is designed to extract the most performace out of your process at the lowest cost, Best Wishes, MJ

To: Maxwell who wrote (26286)	12/1/1997 1:36:00 AM
From: Yousef	Respond to of 1572776

Maxwell, Re: "The answer to Yousef-Ali's debate is ..." So good to see you again Maxwell ... but ... you are wrong this time. Let me explain. Based on benchmark data, the K6 is slightly faster than a P5MMX and slightly slower than a PII at a given frequency of operation. This means that even though the chips are designed differently, the performance is close to the same (averaged over 20 benchmarks). Question, why is the K6 not being produced at the 266mhz and 300mhz bin points in AMD's .35um process. The answer is that the AMD .35um process is not capable of this performance. The reason for this is due to device/FET design. It's that simple and easy ... No need for CPU architecture discussions. Make It So, Yousef PS Someone else changed my profile ... interesting, eh?

To: Maxwell who wrote (26286)	12/1/1997 6:10:00 PM
From: Ali Chen	Read Replies (4) \| Respond to of 1572776

Maxwell: <The bottom line is that all 3 factors interact with each other and often difficult to sort out which is the speed limiter.> This is not so difficult. Let me suggest the following simplified model (for those of us who did not designed too many microprocessors:-). Let the gate in a design (A) has a propagation delay of <G>. Let assume that some logical block in the CPU (A) has to have N gates connected sequentially to perform a certain function (instruction decoder, for example). Let say that this function need to be done in one clock, or by the next clock edge. Then the signal propagation across this logical block would be delayed by about: Del = G + G + G + ... = N*G + interconnection delays. The CPU cannot run faster than F = 1/Del, this is the speed limit. My point is that if you do not know the N, is is MEANINGLESS to discuss how bad is G in this particular PROCESS technology. <It is silly to compare K6 and PII speed because they have different architecture and layout.> I hope you mean "gate design" and not "speed" here: the final CPU speed grade is the selling point (unfortunately). What is really silly is to implicitly ASSUME that the N is the same for K6 and P-II, and pointifically rant about inferior Leff and Idsat of AMD gates. Conclusion: Yousef is MEANINGLESS. Period. Regards, Ali