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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Ali Chen who wrote (26313)	12/1/1997 6:28:00 PM
From: StockMan	Read Replies (1) \| Respond to of 1572777

Buzz(w)ard Ali babble, Re -- pointifically rant about inferior Leff and Idsat of AMD gates. Hey theres a position (Vin Dham's) vacant at AMD. You should apply. A "smart" guy like you would have no problems fixing all of AMD's yield problems. Stockman

To: Ali Chen who wrote (26313)	12/1/1997 6:43:00 PM
From: Maxwell	Respond to of 1572777

Ali: Very nice explanation. But one thought for you is that given the design of K6 has the speed been pushed to its limit with given N gates? The answer is no! There is still alot of room left for improvement in speed. You will see K6-300 soon as demo at Comdex. Maxwell

To: Ali Chen who wrote (26313)	12/1/1997 10:30:00 PM
From: Yousef	Read Replies (1) \| Respond to of 1572777

Ali, Re: "Let me suggest the following simplified model ..." This simple model is for ... simple minds like yours, Ali. This model is WRONG. This does not explain the real world data, let me explain. The PII runs at 25% higher speed than the top-of-the-line K6 (300mhz versus 233mhz). Please post the benchmarks that show that a 233mhz K6 is 25% faster than a 233mhz PII. In fact for FPU, 3D and MMX, the PII is superior by a large margin. This destorys your simple model, Ali. Please stop "babbling" ... you're getting to be as bad as Petz with his inaccurate forecasts!! Make It So, Yousef

To: Ali Chen who wrote (26313)	12/1/1997 11:03:00 PM
From: Bill Jackson	Read Replies (1) \| Respond to of 1572777

Ali, Will not different areas of assorted gate delays all dance to the tune of the clock? As you speed it up you get closer and closer to one chain or another not being able to reach a settled state before the clock lowers the boom and the data error then is fed to the next stage. It may be a fatal error(freeze) or just bad data fed onwards. The settle time will be a function of how many gates etc have to settle and the speed they settle at. Optimal design will minimize the length these serial chains to allow for the fastest possible speed of the CPU. Sort of like cam float. Bill