Michael and Intel Investors - Intel's New Technology Arsenal
Intel has developed two different techniques for adding field programmable/alterable features to their products which are non-volatile - that is, the newly programmed/altered logic retains its logical state even with power removed.
A few months ago, a rumor was circulated that Intel had incorporated features in their Pentium Pro and Pentium II that would allow in-system reconfigurability as far as modifying internal microcode. At the time, not much was made of the technique for reprogrammability, and most people assumed, I believe, that internal SRAM was incorporated for this purpose. Indeed, Intel may have incorporated SRAM (Static Random Access Memory) cells for this purpose, but this memory loses its contents when power is removed - requiring the SRAM to be "reprogrammed" during every power on sequence - a nasty, difficult process since it requires an external non-volatile re-programmable memory to hold the "updated" code. Most newer PCs incorporate FLASH EPROM memory for the BIOS, so the possibility does exist, in principle.
However, Intel's Technology Development group has been working on TWO separate technologies that will permit them to add PROGRAMMABLE AND NON VOLATILE features to their microprocessors. These two technologies are Polysilicon/Titanium Silicide fuses (one-time programmable) and (this is the most intriguing) FLASH EPROM technology in their logic process.
1. Polysilicon/Titanium Silicide Fuses -
During the next week or so, Intel will deliver a paper at the 1997 IEDM (International Electronic Devices Meeting) describing a one-time programmable (OTP) fuse structure incorporating a thin Polysilicon conductor with Titanium Silicide (TiSi2) on top of the poly in a 0.25 micron wafer fab process. It should be noted that a Titanium Silicide film on top of the polysilicon gate has been used by Intel for recent generations of logic processes.
Sourcing a fairly high current through a narrow conductor of this sandwich causes localized heating and melting of the sandwich, creating what Intel refers to as a polyagglomeration fuse (PAF). The Titanium Silicide dissolves the molten poly creating a reduced cross section or gap, greatly increasing the resistance of the fuse structure.
The fuse is incorporated as one leg in a current sensing cell, the other leg containing a reference fuse. The cell can then be used to test the programming fuse before and after programming. Once programmed, the cell will set a logic state from low to high, or enable a signal path previously disabled, depending upon the particular circuit implementation.
Of what use is this capability? A device can be altered (electrically) after wafer fabrication and after assembly into a package and even into a system. Each device can be uniquely serialized to provide a unique code for prevention of counterfeiting or traceability/identification in case of theft. Specific process information and/or test information can be "programmed" into the device such as an optimum Vcc voltage that can then be sent to a programmable power supply for supplying this optimum Vcc in a system.
Microcode modification and patching can also make use of this capability. Further, redundant structures can be incorporated (more on that below) and "programmed" in during test while "programming out" the original features which were non-functional.
Intel is no stranger to polysilicon fuses. These were used by Intel (without any titanium) as the programming element in Intel's bipolar PROM circuits dating back to the early 1970's. The i3601, i3602, i3604 and i3616 were 1K, 2K, 4K and 16K Bipolar PROMS. The latter two were the first multi-layer metal products used on Intel devices. Bipolar products were dropped by Intel in the early 1980s as the speed of CMOS increased to such an extent that the Bipolar process no longer afforded any real advantage, especially in light of the lower circuit density associated with this process (as well as higher power).
2. FLASH EPROM CELLS Embedded in SRAM/Logic circuits.
Intel has developed the capability for incorporating re-programmable FLASH memory cells in their 0.25 micron 512 kilobyte SRAM memory circuits. These cells are used to implement redundancy. For those unfamiliar with redundancy, this technique assumes that some chips on a wafer, each of which may have 4 million bits and 24 million transistors (a 512 Kilobyte SRAM will have 8 bits/byte and 6 transistors/bit), may fail because only ONE or TWO transistors are defective. By incorporating a small amount of EXTRA (redundant) memory bits, the EXTRA bits can be used in place of the defective bits transforming otherwise defective devices into perfectly useable memory chips.
In actuality, memory chips are organized as grids of memory cells arranged in a ROW-COLUMN format. The redundancy makes use of complete EXTRA ROWS and EXTRA COLUMNS, sitting adjacent to the "regular" rows and columns of memory cells or bits. The trick, then, is to test a device, determine if any memory bits are defective, and subsequently DE-SELECT the ROW or COLUMN in which these bits occur. At the same time, an appropriate ROW or COLUMN form the redundancy pool is mapped into the address space of the defective row or column. Accesses to the "defective" memory location are now made to the appropriate redundant row (or column).
A re-programmable FLASH memory bit is used for the programming element. These are incorporated in the address decode circuitry and can be programmed electrically during wafer sort and/or final (post assembly) test.
The ability to combine an SRAM process with a FLASH process comes by virtue of the incredibly thin gate oxides that Intel uses on its 0.25 micron process. These oxides are approximately 45 angstroms thick. Indeed, these are so thin that LOW VOLTAGES are required to PREVENT tunneling through the oxides during normal operation of these circuits. Intel has apparently figured out how to apply voltages high enough to tunnel electrons through the gate oxide (and trap them on a floating polysilicon gate) without damaging the device itself.
What is not clear at this time is the way Intel has transformed its SRAM process into a process suitable for FLASH memory. The oxides are indeed thin enough. However, Intel's standard ETOX - IV process uses a two layer polysilicon stacked gate structure with ONO (Oxide-Nitride-Oxide) between the first layer of poly (used for the floating gate) and the top, control gate. A heavily doped source diffusion is also employed to assist in the tunnel-erase (gate discharge) process. Hot electron injection is used for the programming (gate charging) process. Perhaps Intel has figured out how to use CMP polished oxides and metal control gates - at this point this is pure speculation on my part. A single poly process can also be used and many manufacturers use this process for EEPROM technology (AMD, Altera, Lattice).
Whatever, Intel seems to have implemented some type of FLASH capability in their 0.25 micron SRAM process. Moreover, this process has been the same as their logic process used to make Pentium II and Deschutes processors, except for the extra few metal layers used on the processors which are not needed for the SRAM's.
This will not be Intel's first foray into the use of redundancy. In the early 1980's, Intel was a leader in the use of redundancy when they first incorporated it on 64 Kilobit DRAMs and 16 Kilobit SRAMs.
3. Implications FOR REDUNDANCY
For Intel to make high yielding, high density (and high speed) SRAM's, they need to do this economically. Redundancy is a mechanism for achieving very high yields thereby keeping costs at a minimum. As the Deschutes nears production (February/March 1998), Intel will be able to produce 450 MHz SRAMS for the L2 Cache to go along with their 450 MHz Deschutes in their SLOT 2 packages. Intel has discussed Deschutes devices with up to 2 Megabytes of high speed L2 SRAM cache - representing 4 SRAM chips per CPU chip. Clearly, these SRAM chips must be kept economical to make to maintain high profit margins when most of the silicon in these packages will be SRAM, not the CPU chip! Redundancy will be a key "enabler" technology for this program to succeed.
More importantly, Intel has discussed follow-on Deschutes chips for the lower cost sub $1,000 PC market. (This differs from a sub-zero PC, the kind from AMD and Cyrix which produce SUB-ZERO PROFITS ). Specifically, a chip (Mendocino) with built in L2 cache of 128 Kilobyte or 192 kilobytes of SRAM as part of the CPU chip itself is part of Intel's roadmap. How can adding memory reduce costs? Frankly, it can't. BUT - if Intel uses the FLASH EPROM redundancy capability, they will be able to minimize the cost of these CPUs + L2 Cache chips by keeping yields high via the use of redundancy.
4. Intel's TECHNOLOGY Advantage(s) over AMD
This use of redundancy can be a strategic advantage over AMD which has announced their own plans of using a whopping 256 kilobytes L1 SRAM as well as attached L2 SRAM in various upcoming variants of their K6 CPU chips. This is an attempt to goose up their lagging performance due to wafer fab process marginalities and some circuit design trade-offs (Floating Point Execution). Recently, AMD has had a minor problem or two with yields leading to their $67,000,000 Q3 loss (before a tax credit). Now, AMD will be shrinking their die by transitioning to a 0.25 micron process but inflating it with the addition of more memory - and many more transistors. These extra transistors will impact yields even further.
The same could happen to Intel - but if (that is an IF) they incorporate their redundancy technology in their newer CPUs, they may be able to enlarge the memory sub-systems while keeping yields in their traditionally high end of the spectrum. As AMD and Intel fight it out for performance and cost, redundancy could offer Intel a formidable tool in its technology arsenal to deal yet another financial blow to Jerry's struggling company.
Paul |
