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To: Petz who wrote (2814)	12/9/1997 8:56:00 PM
From: Yousef	Respond to of 6843

John, Re: "Does anybody know if Intel has ever used or intends to use "local interconnect? ..." Yes, I know the answer to this question for both Intel's .25um and .18um generations. Make It So, Yousef

To: Petz who wrote (2814)	12/9/1997 11:31:00 PM
From: Paul Engel	Read Replies (2) \| Respond to of 6843

Petz - Re: "Does anybody know if Intel has ever used or intends to use "local interconnect"? " Many, many years ago, Intel used a process called "buried contact", which allowed the polysilicon gates to connect directly to diffusion (source/drain contact areas). This accomplishes the same thing as local interconnect. In fact, this process gave them very compact cell sizes for SRAMs. As you know, Intel's 0.35 micron and 0.25 miicron processes do not use local interconnect - and their resultant die size is larger than the comparable AMD K6 devices. But as you also know, die size is only one factor in determining the yield of good devices. AMD made a bet and so far seems to be on the losing end of that gamble. As for Intel's 0.18 micron process, I think they are forgoing the local interconnect once again, and opting for 6'th layer of metal along with some fancy processing of the contacts. By the way, Intel's 0.25 micron process uses C4 processing. In fact, Intel does this processing themselves - all of it. That puts Intel way ahead of AMD - who sends their wafers to IBM for the C4 bump processing. Paul