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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?


To: Time Traveler who wrote (26844)12/17/1997 7:55:00 PM
From: Petz  Read Replies (1) | Respond to of 1574260
 
JYWang, re<95mm Tillamook die size> - this number came from Paul Engel: techstocks.com
Previously, I had thought the Tillamook was 80 mm^2, but even that's only a 1/3 shrink from the P55C, whereas AMD achieved a 58% reduction.

So you DON'T THINK the local interconnects tell the whole story but DO THINK die size tell the whole story. Could you elaborate on this DON'T THINK and DO THINK?

AMD used local interconnects on both the 0.35 K6 and the 0.25 K6, so local interconnects cannot explain why the K6 (0.35) has 2.38 times the die size of the K6 (0.25), while the P55C (0.35) has 1.26 times the die size of the Tillamook (0.25).

Is the poor improvement in die size for Intel the result of not doing a full re-layout like AMD did or is it because of some other weakness in Intel's 0.25 process? Or does local interconnect give greater improvement as the process size is shrunk? I don't know, I'm asking you.

Petz



To: Time Traveler who wrote (26844)12/17/1997 8:29:00 PM
From: Brian Hutcheson  Read Replies (3) | Respond to of 1574260
 
John , why do you have to complicate matters ?
The cost of the die is purely related to how many dies you can make of a wafer . In the case of K6 on .25 it is 380 gross dies , how many for the Oregon cheese ?
Brian