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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: kash johal who wrote (26955)	12/19/1997 1:41:00 PM
From: FJB	Read Replies (2) \| Respond to of 1573930

Kash, RE:I understand their is a new PII coming out for the segment zero market without cache. it's die size probably will be less than 75mm2. Whether Intel pulls the L2 cache out of the PII module is irrelevant to the die size of the PII. The PII is 131mm&#178 on Intel's 0.25 process. Where do you keep getting this 75mm&#178 number from? Bob

To: kash johal who wrote (26955)	12/19/1997 2:35:00 PM
From: Petz	Respond to of 1573930

kash, re:<I understand their is a new PII coming out for the segment zero market without cache. it's die size probably will be less than 75mm2> The "segment 0 cacheless P2" will use the SAME DIE, but there will not be a separate L2 cache chip in the "thermal brick" SLOT 1 module. In fact the P2 die size (131mm) which needs to be mounted in a big SLOT 1 module is much bigger than the K6-3D 81 mm die and runs at comparable clock speeds and has no 3D extensions to the instruction set. In fact its even larger than the K6+3D which has an L2 cache built into the chip. This chip is effectively the same as an entire Intel SLOT 1 module integrated onto a single chip which is smaller than the Deshutes processor chip only (no cache) from Intel. Petz