To: Aaron Cooperband who wrote (44849 ) 1/12/1998 3:49:00 PM From: Paul Engel Read Replies (1) | Respond to of 186894
Aaron - Re: " What is it about local interconnect that allows AMD/IBM to achieve this higher density, " In many circuit layouts, polysilicon gates need to be connected to adjacent (or near-adjacent) source/drain diffusions.(The poly and adjacent two diffusions form the basic three elements of the MOS transistor.) This layout technique is especially critical for SRAM memory cells (typically using 6 transistors/cell) where two of the the poly gates are cross-connected to the opposing diffusions of the other transistor. This polysilicon gate-to-source/drain diffusion connection can be done very densely - without using a poly contact or a diffusion contact or any interconnect metallization - when a "local interconnect" is used. In this process, after the poly gates are defined and the source-drain implants (for doping these regions) are done, the device is masked to open up oxide windows in the protective oxide over part of the gate and over the appropriate source or drain diffusion. AMD connects these regions by depositing a thin film of tungtsen over the wafer and then photomasking/etching the tungsten to remove all the unneeded film - leaving short patterns of tungsten connected to poly gates and nearby diffusions through the "windows" that were etched in their respective oxide coatings before the tungsten was deposited. This technique saves space. If normal contact/metallization is used, the source/drain regions need to be enlarged to allow for contact misallignment (same with poly contacts), and the contact to gate and contact to diffusion edge design rules have to be observed, making for a larger layout. These design rules require that the region being contacted is larger than the contact itself - again to avoid major misalignment and subsequent etching problems. Intel has studied these techniques (they used to use a process called "buried contacts" - discussed in "Intel Inside" - many years ago which accomplished the same thing. To date, Intel has decided the layout benefits do not compensate for the technical difficulty - as verified by AMD's yield problems. Intel will be adding a 6'th layer of metal in the 0.18 micron process to assist in achieving smaller devices. Re: " Would you recommend this book or is there a better one? I recommend the book because it is one (the only one?) about Intel - but bear in mind - there are many, many factual errors, exaggerations and misrepresentations. Believe very little of the details - many of the global issues are conceptually correct, however. For lack of facts, the author has concentrated on personalities - particularly Andy Grove's - and mostly he presents a slant that could be characterized as "unkind". For technical and financial details, manufacturing insights, etc. - you won't find them in this book. Paul