SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Cymer (CYMI) -- Ignore unavailable to you. Want to Upgrade?


To: FJB who wrote (12617)1/15/1998 12:30:00 AM
From: Yakov Lurye  Read Replies (1) | Respond to of 25960
 
Re: 64Mb ramp and .25um

Bob, I am no specialist, but most of 64Mb chips produced now are done without .25 (I am pretty positive about MU line), and many major DRAM manufacturers claim that they are ready for the ramp up. To this extent, immediate ramp up does not require .25mu. Non-DRAM chip makers interested in system-on-a chip like applications could benefit more from .25 installations than the 64mb DRAM makers.

This does not directly contradict your timetable, but seems to limit DRAM-related .25 installations to second-tier DRAM producers and to 128mb/256mb pilot lines at major DRAM companies - work on 128+ mb chips is bound to speed up as soon as the 64mb transition takes place. If 16Mb prices stabilize at current levels, the crossover is expected to occur by mid-year.

Hope you are right though

Regards,

Y.





To: FJB who wrote (12617)1/15/1998 1:28:00 AM
From: James Word  Read Replies (1) | Respond to of 25960
 
Rober RE: 64Meg DRAM and DUV.

"Without a true 0.25um process, the die size of a 64Mb is around 200mmø. "

That's 2 die per stepper field. Not bad, but if the 0.25um shrink
scales area by 50%, then you'd get 100mm2 area and 4 die per field.
That's an incentive.

"What are the flaws with this simplistic analysis James?"
It's probably essentially true. 1 DRAM generation is equal to 1 process shrink, so if 16Meg was 0.35um then 64Meg should be 0.25um.

I think that the only catch is that within each generation of
memory density lies around 3 different shrinks. For instance
a first generation 64Meg may start at 0.30um, 2nd generation 64Meg
may shrink to 0.25um while 3rd generation 64Meg might be 0.22um.
I'm not a DRAM expert but I think that's correct.

Don't forget that DRAM manufacturers are the ones pushing i-line
below 0.35um down to 0.25um with Phase Shift Masks and Off Axis Illumination, and, alas, no Cymer laser.

James Word



To: FJB who wrote (12617)1/15/1998 7:05:00 AM
From: Maxwell  Respond to of 25960
 
.25um Excimer Laser in Production:

To implement the excimer laser stepper in the manufacturing process the company must characterizes the optics, resist and processes (including etching process to prevent from overetching the resist). It takes a few months to do this. Intel may be lagging the pack. I know that MOT, IBM, AMD, and Samsung are using it in production. Companies that will ramp up include TSMC, USM, TXN, etc.

The advantage of excimer over UV bulbs are clearly there including throughput and linewidth precision. It will be a matter of time before everyone implement excimer technology. In the meantime Intel will have to utilize all the old Micrascan they bought.

Maxwell