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To: Petz who wrote (3893)	1/16/1998 1:40:00 AM
From: FJB	Respond to of 6843

Petz, RE:I don't think it would take them six months to come up with the PII-sx if all they were doing was removing the L2 cache from the module. I think the only reason for waiting that long is the ramp to the 0.25&#181m process. Does that sound reasonable considering the die size at "0.35"? Bob

To: Petz who wrote (3893)	1/16/1998 1:42:00 AM
From: Robert Walter	Read Replies (2) \| Respond to of 6843

John, If I am not mistaken I read some where that the PII-SX may not even use slot one but use some form of a socket. Maybe they are going to retrofit it to fit socket 7. Robert

To: Petz who wrote (3893)	1/16/1998 2:02:00 AM
From: Investor A	Respond to of 6843

John, I don't think it would take them six months to come up with the PII-sx if all they were doing was removing the L2 cache from the module. You better believe that Intel would definitely need such a long long time for a simple chipset WITHOUT BUGS! Once again, they don't have anyone to copy from on this PII cacheless chipset. The street talks said that Intel demo such a chipset in Taipei computer show a few weeks ago. It would take Intel a bit longer to develop anything new, even junk staff, when they could get the easy free copy.

To: Petz who wrote (3893)	1/16/1998 2:06:00 AM
From: Elmer	Read Replies (1) \| Respond to of 6843

<Another possibility is that they will add stuff on the PII-sx to make it seem to the BX chipset that it has L2 cache -- this kludge would allow them to avoid designing a special chipset for the beast.> Like what? The P6 generation chipsets have no concept of cache so just what is it that could make it look like there was one? EP

To: Petz who wrote (3893)	1/16/1998 11:59:00 AM
From: Ali Chen	Respond to of 6843

Petz:<I'll bet Intel will double the L1 cache on the castrated "SX" Pentium II in 2nd half of '98. This, combined with 100 MHz bus speed may make the speed penalty about half what it would be otherwise. I don't think it would take them six months to come up with the PII-sx if all they were doing was removing the L2 cache from the module.> Adding more L1 cache would require some serious chip redesign/layout. Bigger L1 cache may add more propagation delays and address/assocoativity decoder delays, which may also lower the upper chip frequency. I feel six months is not enough for this job unless they started this design sometime earlier, as a spare variant. On another hand, the cacheless P-II does not necessarily mean the L2-cacheless system. Who knows, maybe they are planning another Slot 1/SX, and MB vendors will put the L2 cache on MB as in old times. Just a guess. Regards, Ali