FOR RELEASE January 19, 1998
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CLEAR LOGIC CONVERTS ALTERAr FLEXr 8000 DESIGNS TO LASICT DEVICES IN A WEEK, WITH NO NRE AND UP TO 50% COST & POWER SAVINGS
SANTA CLARA, CA, JANUARY 19, 1998 - Santa Clara, California semiconductor startup, Clear Logic, today announced its first family of laser-configured ASICs, the CL8000 Series of LASICs. The CL8000 family supports direct ASIC conversion of Altera (NASDAQ: ALTR) FLEX 8000 designs with absolutely no re-design or re-synthesis, no NRE charges, no minimum orders, and no customer involvement in test vector generation.
CL8000 prototypes are available within a week of receiving the bitstream and volume production is available in three to four weeks. Clear Logic generates test vectors with 100% fault coverage at the factory and fully tests devices prior to shipment. The cost and power consumption of CL8000 devices is as much as 50% less than their FLEX 8000 counterparts.
CL8000 Devices Are Designed Only For The Conversion of FLEX 8000 Designs. They are not general purpose gate arrays. Gate array architectures consist of a "sea" of individual logic gates, while both CL8000 LASICs and FLEX 8000 FPGAs have highly structured logic elements that provide the equivalent of as many as 23 gates each. Converting a FLEX 8K design to a sea-of-gates implementation means all the design information that has been developed during the FPGA design must be discarded. The designer must revert to the original VHDL description or schematic, re-synthesize, re-simulate and perform new placement and routing iterations. Since the basic characteristics of the FLEX 8000 architecture are not reflected in a high level logic diagram or VHDL description, the net list cannot accurately represent the timing of the original design. The designer must essentially start the design process from scratch.
For example, the high level logic diagram cannot represent the timing relationships as they are actually implemented in the FLEX 8000. The timing is dependent on physical implementation. Logic implemented in the 4-input LUT of the FLEX 8000 is deterministic. However, the timing for that same logic in a gate array will depend on how the logic is reconstructed by the synthesis tool. In fact, each time the design is synthesized, the timing relationships change. Consequently, converting FLEX 8000 designs to general purpose gate arrays usually results in timing problems.
Rather than attempting to force a FLEX 8000 design into a sea-of-gates array, Clear Logic has developed a unique logic architecture that directly supports conversion from FLEX 8000 designs. Like the FLEX 8000, the basic logic element of CL8000 LASICs is a four-input look-up-table with a register. These logic elements are arranged in blocks called Logic Building Blocks (LBB). An express bus between the LBBs serves a comparable function to Altera's FastTrackr and the pin-outs of the two families are identical. As a result FLEX 8000 logic designs can be ported directly to CL8000 devices without modification.
ClearShotT Bitstream Extraction and ClearFireT Laser Configuration Result in Ultra-fast ASIC Turn-around. Clear Logic handles the entire conversion at the factory. The company's ClearShot EDA tool extracts the FLEX 8000 bitstream and converts it to laser configuration instructions that result in functionality, internal timing and electrical characteristics that are identical to those of the FLEX 8000. Bitstream extraction and conversion take less than an hour. Since laser configuration is the last stage in the wafer manufacturing process, LASIC prototypes are ready within a week and production quantities can be produced in three to four weeks. The ClearFire laser configuration process allows each die on the wafer to be configured individually. As a result, unlike gate arrays, there is no minimum order quantity. The minimum order can be a single unit.
NoFaultT Automatic, Embedded Test Capability - All test vectors are generated at the Clear Logic factory using Clear Logic's NoFault embedded test capability. NoFault's test vector generating routines automatically generate test vectors, based on the bitstream, that are customized to the FLEX 8000 design and provide 100% fault coverage. The design is segmented into small blocks, called TestCellsT that easily handle difficult to test logic, such as long chains of counters. Each TestCell has three scan registers that can be scanned through the I/O pins. All CL8000 LASICs are fully factory-tested on the wafer and after packaging. As with a standard product, the customer is in no way involved in any testing-related activity.
Smaller Die Sizes, More Routing Resources, Less Power Drain - The CL8000 uses a single laser fuse to replace the six transistors per configuration element required for the storage of the FLEX 8000 programmable routing and switching configuration. More than half of the die size of a FLEX 8000 device is attributable to routing and switching configuration. Since laser fuses require less silicon to perform routing and switching functions, the total die size of CL8000 LASICs can be as much as 50% smaller than that of its FLEX 8000 counterpart -- in spite of the fact that the CL8000 also includes embedded test circuitry and more routing resources.
50% Less Power Drain - The transistors in the FPGA configuration elements draw power and contribute to the notoriously high power drain of programmable devices. Laser configured fuses, on the other hand, consume no power with the result that CL8000 LASICs draw half as much power as FLEX 8000 FPGAs. Any design that is implemented in a CL8000 will draw less power than it did in the FLEX 8000.
Power constraints may limit the amount of logic that can be implemented in a single FLEX 8000. This situation results in having to use larger or multiple FLEX 8000 FPGAs. The inherently lower power drain of CL8000 LASIC devices allows them to implement many power-limited FLEX 8000 designs. Thus, CL8000 devices can be used for logic designs that would fit into FLEX 8000 products, but cannot because they violate Altera's maximum power specifications.
CL8000 LASICs Provide A Practical Cost Reduction Path For Low-volume and Short Product-life-cycle Designs. According to Al Huggins, Clear Logic president and CEO, "General purpose FPGAs, like the FLEX 8000 offer quick time-to-market and the ability to implement design iterations very quickly. Designers pay for this flexibility with higher power consumption and higher prices. Low density FPGAs are two to three times more expensive than masked-ASICs. "In order to reduce costs, designers often plan to prototype with a FLEX 8K device and then convert to a masked-ASIC," Huggins explained. "Unfortunately, trying to fit a FLEX 8K design into a conventional sea-of-gates architecture is like trying to force a square peg into a round hole. The bitstream implementation of an FPGA design is completely different from a net list. The timing characteristics of the internal elements of the FLEX 8000 will not be reflected in the ASIC routing, and race conditions or other timing problems usually result.
"Because of these differences, FPGA-to-ASIC conversion requires the design to be pretty much redone from scratch, requiring re-synthesis and re-simulation that can take one or two months to complete.
"Some designs have product life cycles of less than a year. They don't have three or four months to convert to a lower-cost alternative," Huggins explained. "Other designs don't have sufficient volume to justify NRE charges that can exceed $20,000 per design or to meet minimum order quantities that can be in the tens of thousands of units. Gate array vendors sell lots of 24 wafers at a time. With larger wafers and smaller process technologies, minimum order quantities are only getting larger. As a result of these life-cycle and volume issues, thousands of designs haven't had any reasonable cost-reduction path, until now.
"Clear Logic brings the cost and power savings of ASICs to FLEX 8000 designs that have had product life-cycles that were too short or volumes that were too low to make ASIC-conversion a realistic option. Uniquely, we have provided an architecture and manufacturing technology that simplify FLEX 8000-to-ASIC conversion by offering compatibility with the source design. Essentially, we provide a square hole that is specifically architected to be compatible with the FLEX 8000's square peg. By doing this, we have eliminated the obstacles associated with he conversion of FLEX 8000 designs to ASICs," Huggins concluded.
Packaging, Pricing and Availability - Four-thousand gate CL8452A devices are available now in 84-pin PLCC, 100-pin TQFP and 160-pin PQFP packages. The 160-pin PQFP CL8452AQC160-4 is priced at $14.50 for 100 units. The PLCC CL8452ALC84-4 is priced at $10.40 for 100 units.
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Clear Logic, Inc. was founded in 1996 to offer a no-NRE, quick turn-around cost reduction path for designs that have been implemented using FPGAs. The company employs a proprietary process that converts the FPGA design to an ASIC. Clear Logic has none of the NRE charges or minimum order sizes that are typically associated with ASICs. Clear Logic devices are guaranteed to function identically to their programmable counterparts with no timing problems. Clear Logic is privately held. Integrated Device Technology, Inc. (NASDAQ: IDTI) is a major investor.
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Altera and FLEX are registered trademarks of Altera Corporation. FastTrack is a trademark of Altera Corporation. Clear Logic, LASIC, ClearFire, ClearShot, TestCell and NoFault are trademarks of Clear Logic, Inc. |
