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To: Adrian Wu who wrote (4019)	1/22/1998 10:43:00 PM
From: Time Traveler	Read Replies (1) \| Respond to of 6843

Adrian, "The Deschutes with full speed L2 is not for Slot 1, but for Slot 2." You may be right on this one, but can you prove it by providing us with a link or something? ".a 400MHz PII with a 200MHz L2 cache will be faster than a K6-3D/400/100.....Until the K6+3D arrives with a full speed L2 cache." By the time when AMD has L2 incorporated into the processor silicon, Intel would have them out months ahead. This has been the historical trend! Don't underestimate Intel! "Once AMD can manufacture the K6-3D reliably with the 0.25 micron process, it will have a cost advantage." You sound like Albert Kovalyov, Jack Dlugach, Brian Hutcheson, Maxwell, etc. earlier '97 regarding the K6. What happened? Once Intel phases out Socket-7 for good, no big MB makers would, in the right of their minds, continue supporting Socket-7. Remember Intel has over 85% of the x86 market! "The K6 core is actually more advanced than the PII'2. (6-issue RISC with 64KB L1 vs. 5-issue RISC with 32 KB of L1)" You are too narrow-minded. What you have mentioned does not demonstrate the superiority of a processor from another. The question here is "How much longer do we have before the world migrate to Slot-I?" "This means the release of the cache-less PII will probably turn out to be a major embarassment for Intel," Well, this is a marketing decision. Again, do not underestimate Intel, especially in Intel's marketing arm. And again, Socket-7 will pass. Gradually, Slot-I is replacing Socket-7, just like 80286 replacing 8086, 80386 replacing 80286, 80486 replacing 80386, Pentium replacing 80486, and P/MMX replacing Pentium. Have you noticed Intel has already predicted lower profit margin in the year to come? Well, because of this total transition to P-II. That means Intel would cut the price of P-II so much that there is absolutely no price advantage of K6(?), and we all have to pay a last fair-well to K6 family. History shall remember K6 as an ill-fated attempt for AMD to challenge Intel's dominance in the x86 arena. John.

To: Adrian Wu who wrote (4019)	1/22/1998 11:07:00 PM
From: Paul Engel	Read Replies (3) \| Respond to of 6843

Adrian - Re:"The Deschutes with full speed L2 is not for Slot 1, but for Slot 2. " No - I think the full speed L2 cache will be available in both slot configurations. Re: ". We don't even know what chipset will be used with Slot 2 yet." You don't know - but I do. It's the 450 NX (Orion 2). Now we both know. Re: "is the stopgap chip until the Merced arrives. " Get serious. Intel will have the Deschutes, Mendocino (Deschutes + L2 cache on the CPU silicon), Katmai (Deschutes with 70 new MMX instructions) and Willamette - all in the IA-32 roadmap - separate from the Merced. Re: "Until the K6+3D arrives with a full speed L2 cache." We are all waiting. I'm sure AMD would love to crank that one out. If their 0.25 micron process tops out at 266/300 MHz, they may be in a world of hurt - independent of their inability to make their Kx's in high yield/volume. AMD offers lots of promises. Eventually they need to ship results. Paul