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To: Paul Engel who wrote (4023)	1/22/1998 11:58:00 PM
From: Kevin K. Spurway	Read Replies (2) \| Respond to of 6843

Re: "No - I think the full speed L2 cache will be available in both slot configurations." Paul, maybe you didn't read the article you posted right above the post I'm quoting. The last paragraph seems pretty definitive to me: exchange2000.com Pentium II Processor Design Enhancements Robert Colwell Microprocessor Forum "However, these fullspeed caches require fullspeed electricals. The other piece of Slot 1, I forgot tell you it runs at half speed to the cache, and that's another reason why the cache chips don't cost as much. But for the servers you want to run them at full speed. For server workloads it makes a big difference."

To: Paul Engel who wrote (4023)	1/23/1998 3:23:00 AM
From: Adrian Wu	Read Replies (3) \| Respond to of 6843

paul: Has there been a change in Intel's roadmap again? I thought the new Deschutes with the full speed CSRAM (as opposed to the BSRAM which only runs 1/2 speed) can only use the slot 2 and a 450NX chipset. This configuration is aimed at servers and high-end workstations. See techweb.com Tha Willamette will be released at the same time as Merced (that's the plan at least). Until then, the Deschutes (and Katmai) with slot 2 will still be for servers and workstations. The Katmai with the new MMX2 instruction will be initially aimed at the corporate market. It will go into both Slot 1 (with 1/2 speed L2) and slot 2 (full speed L2), and eventually replace the Deschutes. See techweb.com Please supply more detail on the Mendocino. There is very little info on the Cacheless PII. Adrian