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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Tony Viola who wrote (28088)	1/23/1998 11:09:00 PM
From: Paul Engel	Respond to of 1574482

Tony - Re: "..you use scan to get to a particular gate or latch input, then you clock or pulse it (through scan) and then look for the appropriate gate or latch output to "wiggle". " Thanks for the description of your test techniques. I think many people think CPUs are simply plugged into a PC motherboard and the system is booted up! If it boots, the CPU is good! Hardly! Paul

To: Tony Viola who wrote (28088)	1/24/1998 12:21:00 AM
From: Bill Jackson	Respond to of 1574482

Tony; From what I read with a CPU the inner logic would not be readily acessable to that kind of scan. A grid like logic array would be more amenable to that kind of test, like a memory would also. Each gate would have some access through some kind of route and could be wiggled. With a cpu you have a number of functional blocks, some of which you can access and can test. Others you must use some internal self test routines, which can be used to test the innards, and which will give some kind of answer to the outside world as go/nogo. The actual fault will not be known, just it fails. Downstream analysis of the faults in an 'autopsy' area might try to find the real bad gate/etc., so they can make look for avoidable faults to up the line yield. With all the routines and combinatorial pathways if you tried to test the entire CPU through all its possible states, and you had 50 million gates of a circa year 2003-5 CPU, even running at 1000 Mhz it would take a while. But tech marches on. They might be able to test more intersections by using field emission probes that could spray electrons to a point, thus putting it in a state, and testing a small part exhaustively. Repeat that over a number of zones. and you could test it all fast. they would need special zones for this tiny type of probe to work, and those would be laid out in the artwork,?? That might be a way to make it into millions of mini tests as you suggest, as that can be automated readily, and if all the gates are OK, it works?, does it? Bill

To: Tony Viola who wrote (28088)	1/25/1998 1:41:00 PM
From: kane	Read Replies (1) \| Respond to of 1574482

< I've gotten away from test in the last few years, but last I looked, Teradyne, based in Boston, and Advantest (Japan) were keeping up pretty well with VLSI testing.> I'm not sure if they are keeping up. I work for a memory company, and we're finding that Teradyne and Advantest (traditional power houses in memory testers) are not keeping up with the speeds. This necessitates having to look at high speed logic testers are not designed with memory in mind. BIST definitely seems the only viable alternative.