Kane, >>I'm not sure if they are keeping up. I work for a memory company, and we're finding that
Teradyne and Advantest
(traditional power houses in memory testers) are not keeping up with the speeds.
Teradyne is not keeping up?????
biz.yahoo.com
SEOUL, South Korea, Jan. 23 /PRNewswire/ -- Teradyne, Inc. (Nasdaq: TER - news) demonstrated its
capability for testing complex systems on a chip on the J973 VLSI Test System at Semicon Korea here
this week. The demonstration featured Teradyne's software tool suite for testing advanced
microprocessors, including those with embedded memory, analog, and scan cells and high-speed
interfaces.
The J973 tests complex systems on a chip with up to 1,024 pins, at clock rates up to 800 MHz and data
rates to 800 Mbits/second. Its Pattern Integrator(TM) architecture interleaves memory, logic and scan
patterns, synchronized with analog resources, for fast, efficient testing of systems on a chip. The system
also provides the frequency and accuracy required to test devices incorporating high-speed memory
interfaces such as Rambus. Since the J973's introduction in 1996, approximately 50 systems have been
ordered. Customers include AMD, Texas Instruments, NEC, and Silicon Graphics, Inc., as well as other
large microprocessor manufacturers. Teradyne's VLSI Test System Customers in Korea include
Samsung, LG Semiconductor, and Anam Semiconductor.
The J973 enables the testing of advanced systems on a chip by integrating specialized capabilities
needed by particular device types:
High-Speed Interface Testing. In the dual transmission line mode, the 1973 reduces
compare-to-drive delays to zero. Testing at the full 800 megatransfer data rate, which is
selectable on a pin-by-pin basis, the system has no dead cycles and zero round-trip transmission
line delay. These capabilities provide the performance needed for high-frequency bus interfaces
such as those provided by Rambus.
800 MHz Clock. An 800 MHz clock provides the drive for at-speed functional testing of the
newest high-performance microprocessors that use differential clocks to achieve high
performance. The low jitter of the J973's high-speed clock allows Minimum guardbands for
highest yields.
Pattern Director. For devices with complex logic patterns, the Pattern Director cuts the time for
silicon debug and production test by managing the execution order of stored test patterns. This
innovation allows pattern sequences to be changed quickly and easily during design verification
without reloading test patterns. The Pattern Director makes it simple and fast to identify
sequence-dependent faults, and allows looping or random execution of any set of patterns without
dead cycles.
Embedded Memory Testing. For embedded memory testing, the J973 reduces the time to achieve
maximum yield. Because some of the most common failures in many VLSI devices are faults in
embedded memory cells, high quality memory testing is critical for these devices. To ensure
sufficient fault coverage while minimizing pattern storage, the J973 provides hardware-based
algorithmic pattern generation. It also provides a Fail Map Memory for real-time storage of fail
data and uses the Data Searcher hardware compression technology; both of these design
innovations speed up the creation of bitmaps for debug and characterization. For embedded
RAMs with redundant cells, Teradyne's patented RA/Plus(TM) Redundancy Analyzer software
quickly determines the fastest, most efficient repair solution.
In addition, the J973 is unique in offering three access modes to test embedded memory, to support
whatever mode the memory design employs. These modes include interleaved access through a logic
address/data bus; direct access to the RAM through a test mode; and, in addition, for devices that have
only a single-pin serial access to the memory, complex algorithmic patterns can be sent to the device
through the new patented Memory Serializer. The J973's Memory Serializer(TM) can deliver pattern
data in any order, with address and data information interspersed in any combination; this patented
technique provides the necessary fault coverage while simplifying the programming of memory tests for
serial scan devices.
Scan Testing. For devices with scan capability, the J973's Pattern Integrator Architecture
provides the Scan Manager(TM) reconfigurable scan memory. The Scan Manager provides a
large pattern capacity that can be reconfigured to fit any device or scan design, with scan testing
assigned to any device pin. The result is full fault coverage to meet a wide range of requirements.
Scan data is interleaved with logic patterns for fast production testing.
Synchronized Analog Test. To test embedded audio and video cells, the J973 offers analog
waveform generators and digitizers integrated in the test head. These analog instruments are
based on Teradyne's world-leading A500 analog and mixed-signal test systems, and provide
high-fidelity waveforms synchronized to digital test patterns. Like other J973 tests, analog tests
are programmed with production-optimized test templates for easy programming and fast test
execution.
The J973's Pattern Integrator Architecture facilitates field upgrades to add these capabilities, thus
minimizing the customer's capital investment, Stewart said.
Teradyne is a leading manufacturer of automatic test equipment and connection systems for the
electronics and telecommunications industries, with headquarters in Boston, Massachusetts. The J973
system is produced by the VLSI Test Division in Agoura Hills and San Jose, California. Teradyne is
listed on the New York Stock Exchange (Symbol: TER). Sales in the first three quarters of 1997 were
approximately $875 million.
Perfect Dock, Pattern Integrator, Pattern Director, Memory Serializer, RA/Plus, and Scan Manager are
trademarks of Teradyne, Inc.
SOURCE: Teradyne, Inc.
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