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To: Joe NYC who wrote (24077)	2/25/1998 1:27:00 AM
From: Craig Freeman	Read Replies (2) \| Respond to of 33344

Jozef & Scumbria, we seem to agree. If you look closely as the 90MHz benchmarks you will see that the speed of a processor does not improve linearly with the bus speed. With a special MB, heavy-duty heatsink and hand-selected memory -- what you can squeeze out of a CPU is, at best, about what you would expect from the next higher clock speed of the same CPU. If it took years before chip makers increased MHz offerings, the bus/AGP race might make some sense. But with everyone readying their 0.25u offerings at ever-increasing native speeds and 0.18u arriving soon enough, the idea of trading cost and reliability for faster bus speeds makes little sense to me. Gimme a GHz CPU running on a good-ol' PCI MB with a 3D board plus gobs and gobs of cheap RAM. They might even have to rewrite Quake ... to slow it down. Craig PS If any of us are posting here a decade from now, there may well be a GHz GXm and a 2GHz Intel Pentium V. When those chips sell for <$100, will we really care about a few extra Winstones? My advice is to out your money into your monitor and speakers ... then enjoy the ride.

To: Joe NYC who wrote (24077)	2/25/1998 8:56:00 AM
From: Scumbria	Read Replies (2) \| Respond to of 33344

RE:"Please explain." Joe, During the past decade there have been two fundamental camps in CPU design. Those that wanted to increase performance through complexity, and those that increased performance through simplicity. Alpha was the ultimate example of a simple implementation. The architects focused on clock rate. M1 and K6 are good examples of complex implementations. Those architects focused on achieving performance by minimizing latencies in the pipeline, at the expense of megahertz, die size, power consumption and time to market. Alpha is far and away the highest performance CPU. It is widely recognized that the Alpha approach was far more sensible. Consumers want high megahertz, low power, low cost CPU's. Glenn Henry, the architect of C6, wrote an excellent piece addressing this concept. winchip.com It would make more sense for the Cayenne design team to focus on changes which increase megahertz, rather than architectural tweaks which decrease instruction latencies. RE:"Even though MediaGX accesses memory differently, memory still runs at it's own speed (83 MHz apparently in MediaGXm), not at the speed of the CPU." There is a lot of discussion on this thread about "bus speeds." The bus that is being referred to, is the bus which connects the CPU to the memory/IO controller (commonly known as the north bridge.) Media GX integrated this bus (and the north bridge) inside the CPU, causing it to run at CPU speeds. MXi will apparently also run this bus at CPU clock speeds. If you believe that "bus speed" is important, you should recognize that the bus you are referring to runs at very high speed inside the Media GX product line. On the other hand, the "SDRAM bus", which connects the memory controller to the memory, will always be limited by the speed of the SDRAM modules, regardless of "bus speed" or chipset design.