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Intel Reveals How Merced Will Retain X86
Compatibility
(03/09/98; 6:37 p.m. EST)
By Alexander Wolfe, EE Times
A just-issued patent and new information from Intel
provide fresh insight into a technical mystery
surrounding the company's upcoming Merced
microprocessor. The question: How can Intel ensure
that the 64-bit Merced CPU can also run 32-bit
software written for X86 chips like Pentium.
Some experts have speculated that Intel would use
software translation. Others foresaw on-chip
conversion via hardware.
But Intel has told EE Times that it will go one step
further in Merced -- using direct execution to run
32-bit instructions, known as IA-32, on its IA-64
EPIC (explicitly parallel instruction computing)
architecture.
"We will provide support for the IA-32 software in
hardware -- it will be hardware execution," said Ron
Curry, Intel's director of marketing for Merced. "It will
execute those binaries directly. It's not any sort of
software translation. It just runs them, just like a
Pentium II would run them."
However, Curry declined to detail exactly how direct
execution of IA-32 instructions on an IA-64 chip will
work. "We didn't build the [Merced] part where
there's a completely separate Pentium II and a
completely separate 64-bit core," he said. "Of course,
we are taking advantage of the hardware that's there
for the 64-bit core. We're doing it in an efficient
manner, and there isn't a translation mechanism, so to
speak.
"Think about it from this perspective," Curry
continued. "If you've got a bunch of hardware on the
chip -- adders and floating-point units -- one way to
execute an [IA-32] instruction set is to completely
duplicate all of those. Well, that's a horrible waste of
silicon, and it's not the most sophisticated way to do
it."
Because Merced will contain many high-performance
execution units on board the chip, Curry noted, "one
of the ways to do [direct execution] is to make sure
that you structure the logic such that you can use it for
both instruction sets."
In technical terms, "direct execution" may be
somewhat of a misnomer, since the IA-32 instructions
have to be manipulated to some extent to turn them
into low-level op codes, which drive actual, on-chip
execution units. Rich Belgard, a computer-patent
expert and consultant based in Saratoga, Calif.,
believes one possible means of accomplishing that
would be to map X86 instructions into native EPIC
instructions inside of Merced.
The technique would have one big advantage in terms
of delivering good performance -- always a concern,
because instruction-set conversion typically entails a
performance hit. Namely, the EPIC op codes would
not have to be translated yet again into
micro-operations. "EPIC instructions are primitive
enough that they can be executed directly," Belgard
said. "All of the really complicated dynamic scheduling
that's done in Pentium II is gone. That's why it can be
much faster than the Pentium II at the native level."
While Merced will take a hardware-conversion tack,
it's clear that Intel is keeping its bases covered and is
investigating a range of technologies for instruction-set
conversion. Indeed, the picture that's emerging
indicates that both hardware and software techniques
may have a place in Intel's plans for a broad family of
IA-64 microprocessors.
"Remember, EPIC is designed to be a highly scalable
architecture," said Belgard. "At the cheapest level, you
do a chip that handles translation in software. At the
highest level, it happens all in hardware."
Plans for a software-based approach are evident in
Intel's new patent, awarded two weeks ago to Leonid
Baraz and Yaron Farber, two Intel engineers based in
the company's Haifa Design Center, in Israel. The
patent, No. 5,721,927, details a sophisticated method
for performing, via software, a binary-to-binary
conversion of one instruction language into another.
"Computer program statements that have been
decoded into machine instructions for a source
instruction set, such as the Intel X86, may undergo a
binary translation in order to be executed on a target
instruction-set architecture, such as a RISC or a
very-long-instruction-word architecture," the inventors
note in their patent document.
"It's definitely a Merced patent," commented Belgard.
"It looks like there's a program running on the target
architecture -- that is, Merced -- to do the
software-translation task in the background."
Belgard characterized the technique as "dynamic
translation," which means that a program is translated
on the fly. "While you're executing the program, the
basic blocks of that program are being translated," he
said. "It looks like there's going to be a task that's
doing translation from X86 to native Merced
instructions inside the processor.
"It's not a fundamental patent," he added. "But it gives
away the notion that they're going to be having a
background task doing translation."
Range Of Options
While the software-translation technique will not be
implemented on Merced, Curry asserted that Intel is
"looking at various types of software translation,
because we want software vendors to quickly get the
maximum benefit out of the new [IA-64] architecture.
"To get maximum performance for some 32-bit
applications, you'll want to run the 64-bit instruction
set, and we want to provide an easy means to do
that," he said.
One technique for accomplishing such translations
would be to run 32-bit executables through a software
converter. Other, more potent software-translation
methods -- such as the one addressed in the patent --
appear to be aimed at on-the-fly conversion of 32-bit
binaries.
Along with direct execution and software translation,
Intel is keeping its other bases covered. An earlier,
widely reported patent sets forth several broader
generic methods of handling two instruction sets on a
single CPU.
One technique noted in that patent is use of a mode bit
to handle dual-instruction sets. Another method
involves the use of a CISC-to-RISC instruction-set
converter. |
