Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Jim Patterson who wrote (50436)	3/10/1998 8:01:00 PM
From: Barry A. Watzman	Read Replies (3) \| Respond to of 186894

>re: "There is no reason for slot one, from what I understand" Actually, I think that there is a reason for it, which is that as CPU speeds increase, the cache memory system had to be uncoupled from the PCI bus to prevent cache performance from becomming a bottleneck. It's not tooooo much of an issue at 233 MHz, but we are headed to CPU speeds upwards of 400 MHz within less than twelve months. The socket 7 architecture becomes more and more of a ball and chain as the CPU speeds increase. The Slot 1 architecture was Intel's response (although I won't argue that they wanted and created a patented architecture that AMD and Cyrix could not use with competitive chips).