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To: Barry A. Watzman who wrote (50440)3/10/1998 9:45:00 PM
From: David S.  Read Replies (1) | Respond to of 186894
 
Barry, I was checking out the G3s from Apple and notice that their
speedy snail does the same thing as the the PII Slot I you mention,
that is, put L2 cache side by side with the processor on a dedicated
"backside" bus. Slot 7 design is a major handicap.

Regards, David S.
Long on Intel, Iomega, Neomagic



To: Barry A. Watzman who wrote (50440)3/11/1998 12:25:00 AM
From: Paul Engel  Respond to of 186894
 
Barry - Re: " but we are headed to CPU speeds upwards of 400 MHz within less than twelve months"

Actually, within 36 days.

Paul



To: Barry A. Watzman who wrote (50440)3/11/1998 1:01:00 PM
From: Jim Patterson  Respond to of 186894
 
re: >re: "There is no reason for slot one, from what I understand"

Have you heard of Super 7?
That is a socket 7 with a separate bus for the L2 Cache all wrapped into one package just like AGP.
Or the silicon could be put on the CPU and stuck into the socket 7.

Bottom line, Slot 1 is just a market grab by Intel.
In an interview in Boot Mag, Glenn Henry, Developer of the Winchip, says that when the Intel's guys are pressed, they really cannot give a concrete reason for it.

Jim