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To: Jean M. Gauthier who wrote (50523)	3/11/1998 8:25:00 PM
From: Pullin-GS	Respond to of 186894

You just described Dual Instruction Set capable. Not Dual Operating System. Actually the new chip is slated to be Instruction Set Compatable with: 1)HP PA-RISC 2)Intel Pentium w/MMX 3)Intel Pentium 4)Intel 80486 5)Intel 80386 6)Intel 80286 7)Intel 8088 8)Intel 8086 9)Partial compatible with 8085, 8080, 8008 I count 9. ;-) Now I'll go on record as saying: Show me a chip made by Intel with an integrated OS (as in disk/network operating system) built into it and I'll eat my hat. :-)

To: Jean M. Gauthier who wrote (50523)	3/11/1998 8:29:00 PM
From: Barry A. Watzman	Read Replies (2) \| Respond to of 186894

The X86 execution of the Merced is NOT being done with software emulation, its done in hardware (in this context, I'm calling microcode hardware, since the IA-64 execution also uses microcode). It's not a separate dedicated "CPU within a CPU", but apparently an alternate "mode" of the CPU's instruction execution unit. Details are sketchy, but some were revealed in a patent application filed by Intel released last week. There was a news article on one of the services that I read (possibly Yahoo or ZDNET), but I can't find it now. Also, Intel does not classify Merced as RISC, CISC or VLIW, they have given it a new moniker which I can't remember right now but I'm sure that Paul will have it. It's closer to VLIW (Very Long Instruction Word) than to RISC, but has some new twists.