Chip-Scale Vs. Flip Chip Battle Rages
From Page One of Electronic News: September 22, 1997 Issue
electronicnews.com
By Bernard Levine
San Jose, Calif.--Even as vital infrastructure emerges daily for new chip-scale packages (CSPs), debate is raging within the semiconductor packaging community over whether the conventionally classified CSPs will become a dominant force for years to come, or instead primarily serve as a stepping stone to more exotic flip chip and other bare die technologies. CSPs seem to have a near-term edge, but the longer term remains a question mark, with many claiming that cost considerations ultimately will decide the winner.
While new assembly gear, materials, packaging and componentry were showcased at Surface Mount International (SMI) here and other recent shows targeting many new technologies, including a major thrust in silicone encapsulation unveiled here at SMI by CSP developer Tessera and Dow Corning, and new flip chip plastic ball grid array capabilities touted by Fujitsu Microelectronics (EN, Sept. 15), the battle of CSPs versus flip chip was fought out in the SMI technical sessions and workshops, and in conversations throughout the San Jose Convention Center. Opinions were diverse, with some championing one technology or another, while others said there would be plenty of future applications for both CSPs and bare die, with varying predictions expressed on which would eventually prove to be lowest-cost for different end-usages and pincount densities.
Analyzing the controversy, Ron Bauer and Steve Greathouse of Intel said here, "The debate continues as to the future direction of IC packaging--whether the industry will move toward a chip-scale package or will everything go to flip chip. The answer is not clear and will not be decided until a few of the issues with flip chip are resolved."
Several Cost Factors
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Package trend drivers, according to Bruce Freyman, VP, business development, for packaging foundry Amkor Electronics, "are cost of the die, cost of the package, cost of the motherboard, size, thickness, I/O count, thermal and electrical." In the SMI keynote speech, Mr. Freyman added, "Ever-shrinking portable systems need lightweight, small-size and thinner packages. Thermal performance demands are generally low."
Discussing "chip-scale vs. direct-chip attach," Mr. Freyman noted DCA issues include "testability (known good die); increased motherboard cost; non-standard SMT technology (underfill is rigid); no common footprint (when multi-sourcing is required)." He added, "Chip-scale packaging solves all of these issues."
At a special Chip-Scale Packaging symposium held during SMI, Tom Chung of Tandem Computers and Claude Hilbert and Masako Robertson of Microelectronics & Computer Technology Corp. (MCC) noted in an update on CSP technology that "in general, CSPs are more user-friendly than direct-chip attach because CSPs are packaged components that can be readily tested and burned-in. CSPs can also accommodate die shrinks resulting from improvement in silicon fabrication techniques while still offering a constant footprint to users. Flip chip or direct-chip attach is the ultimate choice for achieving the smallest possible footprint and the highest electrical performance, but CSPs can come close to the same performance at a lower risk. Future adaptation of high-I/O CSPs will be dependent on the availability of high-density PCBs or build-up substrates at reasonable cost. CSPs appear to offer the best combination of performance and ease-of-handling, and system makers have started adopting CSPs despite the fact that the assembly process and board-level reliability still pose challenges."
In their presentation to the Chip-Scale symposium, Intel's Messrs. Bauer and Greathouse added, "One of the main hindrances to mass conversion to flip chip is the underfill requirement. Underfill must be added under the die to insure added reliability and compensate for the CTE differences as well as protect the die surface from contaminates. Underfill is not an easy process and requires additional equipment, operators, and bake ovens. It has been said that you can either build the package on the board with underfill (like a flip chip) or you can build the package with the underfill in it and then put it on the board. The best answer at this point seems to be to have the underfill as part of the package and eliminate the additional effort of adding the underfill on the board. The MicroBGA package has the elastomer layer which is actually the underfill already in the package."
Intel Comments
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Intel and others have licensed Tessera's MicroBGA chip-scale package, with many earmarking usage in flash memory. Addressing the Surface Mount Technology Association's annual meeting and luncheon, held during the SMI show here, Intel's Peter T. Larsen and George Mello discussed how advanced flash memory packages drive on-board programming innovation. Mr. Mello noted, "The trend is to smaller and smaller packages. The whole industry is embarking on chip-scale packages. There is real strong interest in the customer base." Intel, he said, "just qualified our first MicroBGA; our goal is a million units or more a month as quickly as we can. There is strong, strong interest. Most interest is from the hand-held, telephone and pager market."
Many others here also debated the pros and cons of CSPs and flip chip-bare die packaging approaches. Anthony Close, Motorola director, process technology, Advanced Manufacturing Technology, Cellular Subscriber group, said, "Packaging drives us in the cellular game to CSPs. Will CSPs be competitive with BGA? They already are in some areas. Flash memory, in our business, definitely is competitive. CSPs will be driven by small, portable products, but eventually, all applications will use it, because the cost will be less, like surface mount. Direct-chip attach is the ultimate on many roadmaps. We see people work in flip chip, but some have elected to go backward with CSPs. There is a lot of debate within Motorola. People have come up with different solutions. My own view is DCA will be the technology of choice for certain applications, a niche. It may become mainstream in four to five years, (but until then), CSPs will be more mainstream" over the coming four to five years.
Mobile Phone Producers
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In a presentation on "the future of high-density packaging in personal communicators," Mike Campbell of BPA Group Ltd. of the U.K., said major roadblocks to chip-scale packaging seen by mobile phone producers include "availability of ICs in CSP format; standardization--constructions and pitch; availability of micro via PCBs; reliability and approval; test and burn-in socket availability; experience of using CSPs directly in an SMT assembly line."
Jan Vardamann of Tech Search International noted, "Demand is there. The question is what is available. The real issue is: when will there be more volume.?"
Eying the various packaging alternatives, Bob Marrs, president of start-up Abpac, said, " I think there will be multiple winners, three or four." He added, "We need better standards for CSPs."
Contract manufacturers are gearing up for many contingencies. Michael Marks, chairman/CEO of contract manufacturer Flextronics International, said, "We have to be prepared to do any of them. We don't drive that; we are followers--the customers will design in (the packages), but we must be knowledgeable. "
Stan Drobac, VP and GM of Flextronics' passive and wireless products, said "I'm not sure it is a CSP-vs.-flip chip situation. If you look at various kinds of CSPs, a large fraction of them are built with flip chip technology. The die will be flipped onto some sort of an interposer substrate, and that substrate will then have solder bumps or leads put on and encapsulated to form a CSP. There you have a CSP that is flip chip inside, so the two are not necessarily competitive. The real choice people make is between CSP or bare die, where bare die can be either flip chip or wire-bonded chip-on-board. There won't be a definitive answer, because there are places for both. At Flextronics, for example, we are building volume product with bare die using wire bond assembly, and for those products, it would make no sense to go to CSP, because CSP would only add cost. There are other, more complex products we build, where CSP will be a better choice because of advantages in testability and handling."
Flip Chip Adherents
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Marie Cole of IBM Microelectronics, said, "At the high-performance end, more and more are looking at flip chip."
Mike Petrucci of Compaq Computer said, "There will be a market for both. CSPs are more consumer. Flip chip is offered for low- and high-end use. So many packages are coming out; people are confused. There is a horse race for who will use volume."
At contractor Avex Electronics, H. LeRoy Jarvis, VP, assembly technology and integration, said, "We are trying to take MCM-L, whether wirebond or flip chip, to market. All are going to coexist for some level, because all offer different advantages and performance. People are just putting together capabilities in CSPs. Most contractors and OEMs are looking at it. CSPs are just like BGA, with different pitches and complexities. All will coexist. Cost--it isn't a black-and-white answer right now. It is still formulating. There is low-cost and higher-cost chip scale. As CSPs start to penetrate beyond memory, cost will be higher. There has been an increasing amount of interest in advanced packaging, specifically MCM-L and CSP. It will drive a lot of future deployment. It has been very hot for the last six to nine months."
Martin Goetz, until recently ASAT's director of advanced technology, and now director of packaging technology, Alpine Microsystems, a Campbell, Calif., developer of silicon-on-silicon high-density interconnect technology, focused on graphics, RF wireless, microprocessors and mass storage, offering conventional BGAs and QFPs, said, "In my opinion, CSPs will carry the ball a lot further before people are willing to pay the price for flip chipping. There is still a pretty big argument."
Meanwhile, Eric Samuelson, Electronic Industries Association (EIA) staff director for components, information and industrial groups, said an EIA-, MCC- and Sematech-backed Known Good Die Industry Assessment Workshop last week in Napa, Calif., would "provide the industry with a snapshot assessment of the bare-die infrastructure."
Bob Black, president of ESEC's Zevatech assembly equipment unit, noted, "More and more customers are doing some flip chip or chip-on-board, or chip-scale packaging, such as MicroBGA." He added, "To handle flip chip, you need special nozzles with non-scratch tips. You also need very good control of placement pressure. You also need a good image recognition system." He added: "I think flip chip, bumped die with no package, will be the ultimate winner. You won't get any less than no package." Roland Heitmann, also of ESEC, said, "BGA and CSP packages on the board level will be huge volume in the near future. In some cases, they are already. Flip chip will have more gradual implementation at the board level. At the package assembly level, there is a very strong push to implementing flip chip. Flip chip in the packaging assembly world will be the long-term winner." |
