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To: Maxwell who wrote (5115)	3/20/1998 9:53:00 AM
From: Yousef	Respond to of 6843

Maxwell, Re: "Do you know what is the die size for the PII on 0.25um? Is this a 4 metals or 5 metals process? Does it use C4 bump technology?" The Intel .25um process has 5 levels of metal, a 1.8V FET design and DOES use/support C4 bump technology ... Paul will be getting back to you shortly on the PII die size. Make It So, Yousef

To: Maxwell who wrote (5115)	3/20/1998 2:11:00 PM
From: Paul Engel	Read Replies (1) \| Respond to of 6843

Maxwell - Re: "Do you know what is the die size for the PII on 0.25um? Is this a 4 metals or 5 metals process? Does it use C4 bump technology? As I recalled the PII on 0.35um is about 200mm^2. Die size = 131 sq. mm. Metal Layers = 5 C4 technology is used PLUS conventional AL bonding pads. Once C4 packaging/assembly is up to speed, the Pentium II/Deschutes can be "downsized" by eliminating the pad ring surrounding the Deschutes C4 bumps and core. This will reduce the die soze by 5% or more. Other compactions may also reduce the die size further. Paul