Doug, does this play directly into INVX's system of surface mounting IC's?
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June 09, 1997, TechWeb News
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Two firms put contacts on wafer-bound dice -- Chip-scale steps up as wafers grow legs
By Terry Costlow
San Jose, Calif. - Chip-scale packaging may take off sooner than expected with the emergence of techniques for putting contacts on a chip while it is still in wafer form. The wafer-level work, being performed at two companies, will help vendors take chip-scale packaging beyond low-lead-count devices to more-complex components, in which the space-saving benefits of chip-scale become even more pronounced.
ChipScale Inc., for one, is finalizing technology that will permit the production of ICs, power MOSFETs and integrated passives in chip-scale packages. "One advantage is that with wafer-level processing of our post and beam technology, we can create different size contacts for power, ground and data," said Jim Young, marketing vice president at ChipScale. "We can also do full wafer-level testing without fear that we'll damage the chips. This is much more cost-effective than packaging each of the chips once the wafer is cut up."
Chip-scale packages are only about 20 percent larger than the IC itself, providing protection for the die without adding the bulk of conventional packages. Until now, however, the company has only made headway by signing licenses and helping forge standards for low-lead-count devices with fewer than 28 contacts.
Other chip-scale firms are also turning to wafer-level assembly. Tessera Inc. (San Jose, Calif.), which has licensed its chip-scale packaging to Intel, Texas Instruments, Hitachi and other companies, is also gearing up to put contacts on the chip while it's still in wafer form.
"What happens now is that you can have a wafer fab facility that ships packaged wafers, which saves the fab guys about 20 days in processing," said John Smith, chief executive officer at Tessera. "This also gets rid of a very expensive tester."
If wafer-level production indeed catches on, it may provide several significant benefits to semiconductor manufacturers. Today, for example, many spend a fair amount of time and money, sending die to IC packaging houses in the Far East, sources said.
"Wafer-level assembly makes it really convenient to do packaging, which could be a major benefit for semiconductor manufacturers," said Jan Vardaman, president of TechSearch International (Austin, Texas). "Potentially, they could bring assembly closer to the semiconductor fabs. It will be fairly easy for chip makers to do their own packaging."
None of the licensees of either ChipScale or Tessera is yet producing parts that use the wafer- fabrication processing, however, but both expect to see initial shipments this year. This ramp up will come as chip-scale packaging moves forward swiftly, even though usage in the United States is still only in prototype stages.
"We haven't run our numbers yet, but it looks like shipments will be in the tens of millions this year," said Vardaman. That "is quite an increase over last year, when they were just a few shipments, mostly in Japan," he said. "The big holdup this year will be to get production volume up. Demand is definitely there, especially for flash memory in chip-scale packages."
Most observers and suppliers agree that the main reason system designers turn to chip scale is to pack more into small products such as cell phones, notebooks and video cameras. However, one contract manufacturer who has done a number of prototype boards has found a surprising side benefit beyond size.
"We can place them on boards faster than plastic BGAs or TSOPs because they are small enough to put in a chip shooter," said Julian Partridge, senior R&D engineer at XeTel Corp. (Austin). "This is a self-centering package, so the chip shooter can place them precisely enough even at fairly fine pitches."
Though ChipScale and Tessera are talking about high lead-count ICs, both firms are currently working more with middle-density packages. Most of the chips that will use this new packaging technique will have fewer than 200 leads. However, they are being used in a wide variety of ICs.
"We are starting to ship all types of chips-mixed-signal, ASICs and DSPs-with pin counts of 60 to just shy of 200 leads," said Kurt Wachtler, packaging strategy manager at Texas Instruments' Semiconductor Group (Dallas). "This attacks what is currently going into thin quad flat packs. I feel it will displace TQFPs when it gets cheaper. And I think it can be cheaper when volumes get there. This is a different beast than the plastic BGAs that go into PCs and workstations, which have much higher lead counts."
One reason that chip-scale packages are seeing use mainly in fairly low lead-count applications is that the contacts are fairly close together. That means that routing signal lines to a high number of contacts will be difficult unless a board's line widths are quite fine.
"Chip-scale's real benefit will be in high lead-count packages, but it's only being implemented in low pin counts because people don't know that the line widths they need for higher lead counts are available," said Marshall Andrews, chief executive officer of ITRI (Austin), an R&D consortium in the circuit board industry. "In one year, we've gone from three companies who could make buried vias or 'build-up' boards to 20 who have the capability now."
However, these microvia or build-up board technologies are more expensive than conventional laminate board-plating techniques. That's one of the criticisms some people have leveled against wafer-level contact placement: If leads are produced at that level, it's more difficult to fan them out to a roomier pitch.
"A big problem with chip-scale is that the die size is the same as the package, which means our customer has to deal with pitches of half a millimeter or below," Wachtler said. "That means that they have to use more expensive printed-circuit boards."
Copyright r 1997 CMP Media Inc.
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