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To: Jeff Fox who wrote (51673)3/31/1998 2:15:00 PM
From: Tony Viola  Read Replies (1) | Respond to of 186894
 
Jeff, >>"The chip project "Mendicino" is doing
just this - adding 256KB L2 cache. This is 1/2 the cache size of the PII cartridges. This cache will
be integrated with the processor on a single die and will be presumably much cheaper overall
than the PII cartridge with discrete SRAM chips."<<

Are you sure that the L2 cache for Mendocino will be on the same die as the processor? The other alternative is to put it on the cartridge, as with current PII's. Then, how is it possible to make it so much cheaper than the real PII? You are probably right; the reason I wasn't sure is that a PII, and 256K of L2 sounds like too much for one die. Anyone else?

Thanks,

Tony



To: Jeff Fox who wrote (51673)3/31/1998 2:16:00 PM
From: rob  Respond to of 186894
 
All systems currently have caches... in older Pentium systems
the L2 cache is on the MB, either 256K or 512K. For the Pent-II
this has been put on the cartridge.

For the K6 and Cyrix chips the L2 cache remains on the MB and
frankly you would be har pressed to find a system with out
an L2 cache.

The point of the comparison is given you have $1000 to spend
what's better a Celeron 266Mhz or a K6 266Mhz (configured as
normal with a 512K cache). Well the K6 system kicks butt!

The problem with INTEL is it is trying to use the L2 cache as
the price differential between its high end low end. They
have been doing this all alon with the P6 generation.

Starting with the Pentuim Pro's you had a P6 with a 256K or
512K cache in the same pacakage (and therefore could run at
CPU speed 166Mhz or 200Mhz). Later with the Pent-II cartridge
Intel is used the L2 cache as the price differentiator between 256K
or 512K in this case running at 1/2 CPU speed.

Same game with the Celeron. Intel can use the same die and
sell the same CPU into the market at $600 or $100 depending
on how much L2 cache it hooks up to the CPU.

AMD is wise to this and so are the box makers and they will
exploit this when ever possible. This is the main reason Intel
patented the SLOT interface and brought the Northbridge chipset
controller onto the CPU card. Controlling the amount of L2
cache is "key" to Intel's P6 cpu priceing strategey.

rob