SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?


To: Elmer who wrote (31957)4/20/1998 4:56:00 PM
From: Petz  Read Replies (2) | Respond to of 1578043
 
Elmer, you're probably right that Intel can "make $ but not much" with the Celeron version that has integrated L2 cache, when it comes out. Do you know the die size of this chip?

For comparison, here's the AMD die sizes from the 1997 analysts presentation (Slide 68):
K6 = 68 mm^2
K6-3D = 81 mm^2
K6-3D+ (with L2 cache) = 135 mm^2

I've read that the Intel Deschutes die (0.25 Pentium II)
is 131 mm^2. The Intel Mendocino indeed will be a large chip at a
minimum of 185 mm^2, if they can add the L2 memory as
small as AMD, but perhaps you know the correct number.

Petz