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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Petz who wrote (32058)	4/20/1998 5:27:00 PM
From: Maxwell	Read Replies (1) \| Respond to of 1578147

John: <<I've read that the Intel Deschutes die (0.25 Pentium II) is 131 mm^2. The Intel Mendocino indeed will be a large chip at a minimum of 185 mm^2, if they can add the L2 memory as small as AMD, but perhaps you know the correct number.>> You are pretty close on the actual die size of Deschutes with integrated 256K L2 cache. Because of its big die size, INTC will introduce the Deschutes with integrated 128K first. This die size will probably be about 160mm^2, but by that time INTC will eliminate the bonding pads and go all C4. Thus I estimate the die size will be more like 130 to 140mm^2. The reason AMD was able to get a higher density in the cache area is that they use Local Interconnect as a replacement to an extra metal layer. Maxwell

To: Petz who wrote (32058)	4/20/1998 10:54:00 PM
From: Elmer	Read Replies (1) \| Respond to of 1578147

<I've read that the Intel Deschutes die (0.25 Pentium II) is 131 mm^2. The Intel Mendocino indeed will be a large chip at a minimum of 185 mm^2, if they can add the L2 memory as small as AMD, but perhaps you know the correct number.> I don't but obviously it will be large. What I would like to know is why Intel doesn't do local interconnect. As I understand it, this is where AMD gets such a small die size. For some reason Intel chooses to forgo this option, at a cost of considerable die size. Possible explanations could be faster fab throughput, higher yields or ? I don't think it's because Intel lacks the capability. Anyone else know? EP