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To: Paul Engel who wrote (5800)	4/26/1998 9:18:00 PM
From: Brian Hutcheson	Read Replies (1) \| Respond to of 6843

re. Albert , he just prefers to spend his time on the private AMD thread where the real discussion takes place .

To: Paul Engel who wrote (5800)	4/26/1998 11:39:00 PM
From: Maxwell	Read Replies (2) \| Respond to of 6843

Dr. Engel: I just talked to some experts on Cu dual damascene at MOT. They are currently using that technology to make fast 2ns SRAM for INTC to be used in the PII. The copper process save them about 40% of the steps! The electromigration improves by 1000X. As far as the seed layer, they are using sputtering and deposit about 1000A. However on the sidewall it coats only about 100A! The bottom of the trench is a little less than 1000A. For a trench of .25um and 7000A deep that seed layer makes about 20% of the total volume of the conductor. MOT also used to make their PowerPC but saw so speed improvement. The speed of their chip is design limited. As you can see Cu process is the way of the future. INTC will use it but at a much later date. Maxwell