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Technology Stocks : Adaptec (ADPT) -- Ignore unavailable to you. Want to Upgrade?

To: Starowl who wrote (1774)	4/27/1998 10:53:00 AM
From: w2j2	Respond to of 5944

MILPITAS, Calif.--(BUSINESSWIRE)--April 27, 1998--Adaptec, Inc. today announced its new server-centric Fast Ethernet silicon--the AIC-6915 Fast Ethernet MAC chip. Codenamed "DuraLAN", the AIC-6915 marks the first time that any company has architected network silicon with server performance in mind. Adaptec expects the silicon to be a vital enabler of its success in server NIC markets. "DuraLAN is a critical component in our server NIC strategy and product offerings," said David Mendenhall, marketing manager for network products at Adaptec, Inc. "We now have the hardware, software, and silicon differentiation that make up a complete server NIC, and think our customers will benefit from that powerful combination." About the chip Adaptec's DuraLAN silicon--the AIC-6915--is a Fast Ethernet MAC chip. It features 64-bit PCI support; an in-chip processor; a TCP/UDP checksum engine; 8KB internal buffer; a PCI bus analyzer; and support for Duralink Port Aggregation, Failover, and Server Manager. The AIC-6915 features an IEEE 802.3x compliant flow control mechanism, an IEEE 802.3u compliant 10/100 media independent interface (MII), support for both full- and half-duplex operation, LEDs that are controlled via hardware and software, and an interface to an external 8-bit boot ROM. Advanced features include VLAN support (for Cisco proprietary ISL frame format and IEEE 802.1q frame format), TCP and UPD/IP checksum, two receive queues for different size buffers, and time stamp information of every frame received. Additionally, the AIC-6915 features both high and low priority receive queues, header split to separate header and user data, unique address filtering modes, and a frame processor for in-band frame analysis. The network and PCI system clock are disassociated allowing the PCI bus to sleep while the network is active. Four general purpose I/Os can be programmed separately--input, output, open-drain output, or interrupt input. The chip has two transmit DMA queues for prioritized traffic, 32- or 64-bit addressing. Enhanced DMA features include enhanced resource management to provide better overall bus efficiency through: an enhanced interrupt mechanism, interrupt control, and support for multiple transmit buffer descriptor types. Internal buffer management includes unlimited (limited only by the FIFO size) receive/transmit frame queueing in the FIFO to handle long PCI bus latencies, hardware support for handling transmit collisions and FIFO underruns with no software intervention, and programmable hardware to control transmit FIFO thresholds and to prevent underrun of transmit FIFO and enhance overall system performance. The chip supports PCI local bus specification revision 2.1, Intel PCI bus power management interface, Microsoft device class power management reference specification (OnNow), and PC 97, which implements all the hardware features required by Microsoft's PC 97 design specification. The chip also supports 3.3V and 5.0V PCI signaling. The PCI bus master supports enhanced PCI system memory data read and write commands (memory read, memory read line, memory read multiple, memory write, and memory write and invalidate). The PCI slave supports access from configuration (read/write), I/O (indirect, read only), and memory access spaces. Pricing and availability Adaptec's DuraLAN silicon is available immediately in four new server NICs from Adaptec. OEM agreements for use of the silicon as a standalone product will be considered on a case-by-case basis. More information on all Adaptec network adapters and software is available on the Web at adaptec.com.