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To: Maxwell who wrote (5844)	4/28/1998 2:42:00 AM
From: Paul Engel	Read Replies (1) \| Respond to of 6843

Maxwell - Re: " You can't make 2ns SRAM with Aluminum unless you go to geometry below 0.18um." Intel is making 450 MHz SRAMS with a 0.35 micron process using only 4 layers of Al alloy metallization. ISSCC - February, 1998 sscs.org SESSION SP22 SALON 1-6 22.6 - A 450MHz 512kB Second-Level Cache with a 3.6GB/s Data Bandwidth - 4:15 PM B. Bateman, C. Freeman, J. Halbert, K. Hose, G. Petrie, E. Reese Intel Corp., Hillsboro, OR A 450MHz 512kB 4-way set-associative cache SRAM with 3.6GB/s data rate utilizes a tightly-coupled source-synchronous 72b data bus. The 0.35mm CMOS process with 0.22 mm Leff provides 4 levels of metal. {=======================} Memory devices generally do not place extreme emphasis on interconnect density as do logic devices with massive bussing and control signal requirements. Paul

To: Maxwell who wrote (5844)	4/29/1998 12:17:00 AM
From: Time Traveler	Read Replies (1) \| Respond to of 6843

Maxwell, all the advantages you have compiled regarding this copper technology all lie in the area of process engineering which I am very weak about it. I will let the very knowledge power-houses like Paul and Yousef to cross-check those. My point is that from the circuit point of view this copper technology still has no benefit over the existing processes. Shall we start to count the number of months before some one start to manufacture anything serious using this new technology? Time Traveler