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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Kevin K. Spurway who wrote (32459)	5/5/1998 5:10:00 PM
From: Paul Engel	Read Replies (1) \| Respond to of 1572185

Kevin - Re: "... effectively having three levels of cache (similar to K6+3D). " One of the problems with three levels of cache is that a sequence of "cache checks" has to be done. To fetch data, the L1 cache controller looks into the L1 cache Tag Ram and sees if the required data is present. If it is, then that data is loaded into the instruction/data queue. If the required data is not present in the L1 cache , the L2 cache tag ram is interrogated and if the data is present it is retrieved and loaded into the instruction/data queue. Ditto for the L3 cache. Thus, a COMPLETE cache miss will have 3 delays associated with it before data is ultimately fetched from main memory. With the Pentium II architecture - DUAL INDEPENDENT BUS - it may be possible to interrogate the cache tag rams while CONCURRENTLY fetching the data from main memory. In the event of a complete cache miss from both L1 and L2 caches, the required data will have been retrieved from main memory and can then be loaded into the instruction/data queue. Bacically, too many caches will cause an INCREASE in data access times for many situations. Paul