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To: Pravin Kamdar who wrote (6092)5/12/1998 1:56:00 PM
From: Time Traveler  Read Replies (1) | Respond to of 6843
 
Density is only a secondary concern since you can always count on any chip makers to layout their ICs next to the densest possible, besides silicon is a decent conductor of heat. The die size of the IC thus determines the power dissipation capability. The bigger the die size, the more heat it can channel into the substrate, then to the case, then to the heatsink, then to the ambient (assuming no bottlenecks). Does it not the bigger the cross section of a pipe the more water (per unit time) it allows to flow through? Think of heat as water and power as the flow rate of water.

Most of the time you need to jack up the voltage to run at that desire frequency. For example, K6 on 0.35um needs to run at 3.3V for the 233MHz version. Thus, if heat is a problem limiting our precious speed, then channeling this heat out is indeed a good solution.

For now, the resistance you are talking about mostly comes from the on-resistance of the junction. Reducing the trace resistance thus has very little merit. However, as Yousef pointed out half a year ago, the trace resistance is getting more resistive due to thinner metal traces (same square counts). There is a time very "far" (relative to the rate of technologic advancement) into the future that copper technology would be advantageous then.

Meanwhile, why don't you try to understand the following very simple relationship:

POWER DISSIPATION is proportional to (FEATURE SIZE) * (VOLTAGE)^2 * FREQUENCY.

Time Traveler

Ps. Thanks for the information about the monitors. What do you think of the 16:9 aspect ratio?