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To: shane forbes who wrote (12734)	6/1/1998 8:37:00 AM
From: Paul Lee	Read Replies (2) \| Respond to of 25814

Any thoughts on how important this could be LSI Logic Delivers World's First Modular High-Speed Backplane Transceiver Core For CMOS ASICs MILPITAS, Calif., June 1 /PRNewswire/ -- LSI Logic Corporation, (NYSE: LSI) the world's leading developer of system-on-a-chip technology, today announces the immediate availability of the first modular high-speed backplane transceiver created in CMOS. The HyperPHY(TM) core is the first to allow 32 independent high-speed channel interfaces, with custom logic, in a single CMOS ASIC. A HyperPHY based ASIC consumes as little as one-fifth the power of several GaAs, BiCMOS or bipolar chips performing the same function. The core's modular function promotes flexibility by allowing multiple data transfer channels operating at 622- to 830-Mb/s, or any sub-multiple speed. LSI Logic's improvements in backplane transceiver technology allows greater cost savings, real-estate, and power savings for next-generation broadband telecommunications and networking systems. "The explosive growth of the Internet and the increasing deregulation of the telecommunications industry have created tremendous growth opportunities amongst the hotly competitive telephone operating companies and Internet Service Providers," said Giuseppe Staffaroni, vice president and general manager of LSI Logic's Communications Products Division. "Telecom and networking system customers understand the market need to develop faster, smaller and more flexible systems." "The HyperPHY transceiver core is the only modular CMOS solution that integrates multi-gigabit data transfer rates on a single chip," Staffaroni added. "This solution will enable systems manufacturers to stay ahead of their competition by allowing them to design smaller, highly integrated, multi-gigabit per second systems that are cost-effective, run cooler, and are easier to manage." Five independent building blocks together form the HyperPHY core: * Frequency Synthesizer which generates clocks in the frequency ranges of 622- to 830-MHz, 311- to 415-MHz, and 155- to 208-MHz * Clock Recovery Receiver which recovers data at up to 830-Mb/s * Receive Deserializer * Transmit Serializer * Bias Current Generator In addition, the core's modular architecture provide an ideal solution for solving the backplane bandwidth bottleneck in high throughput ATM or LAN switches, Add-Drop Mux or cross-connect systems. The HyperPHY core is compliant with the CoreWare(R) design program and can be used with other electronic building blocks such as LSI Logic's high speed Hyper-LVDS(TM) and Hyper-PCML 5-Volt compatible I/O buffers, to form complete single-chip, high speed backplane solutions. LSI Logic will demonstrate HyperPHY core at Supercomm '98, Atlanta, June 7-11.