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To: Steve Porter who wrote (27136)6/6/1998 4:09:00 PM
From: Pravin Kamdar  Read Replies (2) | Respond to of 33344
 
Steve,

If Cyrix can find a way to pull it off, Intel's plans to rape Xeon based workstation and server buyers, in order to keep their margins up, will be in jeopardy. They want to charge $3000 for 2 megs of processor speed cache. I'm sure LG and others will sell it for quite a bit less.

Pravin.



To: Steve Porter who wrote (27136)6/7/1998 11:52:00 PM
From: Scumbria  Read Replies (2) | Respond to of 33344
 
Steve,

According to information provided by Paul, Mendocino will access the L2 in less than 10ns. The fastest drams require 25ns for a page hit and 100ns for a page miss. Traditional bus architectures add additional latency to memory accesses because of address/data synchronization across the bus.

By including the memory controller onboard the CPU, synchronization penalties are eliminated. There is no way however to defeat the fundamental latency issues associated with dram. Fast dram access is no substitute for an sram L2 cache. The "ideal" combination is an onboard L2 and memory controller. Intel could build such a processor very easily, however their bone-headed belief that they can kill AMD with slot 1 keeps them from making an intelligent choice in this matter.

In a multiprocessor system an onboard memory controller does not make sense. Instead you want to have very large L2 caches to minimize traffic on the system bus.

I believe that Intel will gradually disappear off the desktop if they continue the slot 1 nonsense. MediaGX is kicking their rear at the low end. K6-3/C6+NB will start pushing them out of the mid/high end market (I didn't include any Cyrix processors because the management has been unable to articulate any coherent plans for the mid/high end.) Slot 1 will be relegated to MP only applications.

It appears that the management at Intel just doesn't have the brains to understand what is happening out there.

Scumbria