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To: Andrew Vance who wrote (14413)6/13/1998 4:12:00 PM
From: Kachina  Read Replies (1) | Respond to of 17305
 
Hello - Andrew and tech followers:
Check out this report.
eet.com

This is a group of Japanese researchers who claim that by process improvement they can cut the cost of FAB to 10% of current using 300 mm wafers. And they can do it in the same space as current Fab installed base. So it can be a retro.

The Japanese are good at this sort of thing. If you have read Shingo and ZQC stuff, you understand why.

My guess is that they will do it, or be at worst 15% of current cost.

Why? A. They gotta. Ain't got no choice. B. The engineering/work culture does this stuff very well.

So - what are the implications for the market?
I think way bullish for 2000. And I wonder, is the current bear mkt in tech stocks a play to crunch the sector to take advantage of this next tsunami? Gotta wonder at the timing of it. Gotta wonder.



To: Andrew Vance who wrote (14413)6/14/1998 10:34:00 AM
From: Steve Smith  Read Replies (2) | Respond to of 17305
 
Does anyone have an opinion on CMOS, ESIO, SQNT, or SVGI?

thanks,
steve