Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : CYRIX / NSM -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (27985)	7/7/1998 2:32:00 PM
From: FJB	Read Replies (2) \| Respond to of 33344

Scumbria, Ritz is right. Bob

To: Scumbria who wrote (27985)	7/7/1998 3:05:00 PM
From: Scott Sterling	Read Replies (1) \| Respond to of 33344

> For x86 it is a more complicated problem and requires more silicon > area, but ultimately the speed paths are the same datapath in all > processors. Wouldn't the larger silicon area require a slower clockspeed? And of course there is always the matter of how increasing the use of pipelining affects overall speed. With x86 you get this huge pipeline which then becomes a liability for overall speed. I think the PII is a good example of the tradeoff between the two. They got the extra Mhz, but not much else. --Scott