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To: FJB who wrote (27992)	7/7/1998 4:58:00 PM
From: Scumbria	Read Replies (1) \| Respond to of 33344

Alpha has been running at very high clock speeds for years, largely due to the architecture/design style/methodology. Robert, Exactly. DEC used a superpipelined implementation for Alpha. Until recently, it was a single pipe, full custom design with very large drivers. There is nothing preventing an x86 design house from implementing those same features and achieving very high clock rates. I fully expect to see such an x86 design within the next few years. Scumbria

To: FJB who wrote (27992)	7/7/1998 7:28:00 PM
From: kash johal	Read Replies (2) \| Respond to of 33344

This whole issue is very complex. Some basic facts: The device logic switching speed(to a first order) is a function of channel length, voltage, temperature, capacitive load, gate oxide thickness and device size(W/L ratio of transistor). So when we get these endless arguments between Yousef and ALI. Yousef, is stating (correctly) that the device speed is a direct function of the channel length 0.25 vs 0.35 etc. Ali goes blue in the face stating (correctly) that chip performance (MAX CLOCK SPEED) is a function of chip design. It is ABSOLUTELY TRUE that in an identical process if you make the transistors larger you gain in performance. It is also true that you want to run your chips at the HIGHEST voltage for MAX speed consistent with the given process. In this case I think you are both correct. 1. Bob, you are right: ALPHA RISC architecture is TECHNICALLY superior for a given process vs X86. The reason is that it does not have the baggage of retaining x86 compatibility. HOWEVER the GAP between X86 vs RISC CPU architectures has been CLOSING every year and with Merced probably will be eliminated. 2. Scumbria, you are correct. It would theoretically be possible to speed up the x86 2-4x in terms of clock speed by additional pipelining. You unfortunately hit several limits: A) Die size becomes excessive and yields drop off exponentially and costs increase accordingly. B) You hit power limits. Power is a direct correlation of clock frequency so you would have something running lets say 4X the clock, 8x the power, and 16x the cost of current device for maybe a 0-20% real world performance improvement. PS a chip that took 16x the power of current devices would be impractical. An example is the WinChip which had a very small die size and architected to low cost as opposed to high clock speed and high cost. This is like arguing which is the better car the Audi A8 at $60,000 or the Lexus LS400 at similar rate. The Audi A8 (ALPHA) is a technical marvel, with leading edge light weight Aluminum body, etc but the MARKET prefers the LS400 by a sales figure of 50 to 1. Regards, Kash J.

To: FJB who wrote (27992)	7/8/1998 11:46:00 AM
From: Frank	Respond to of 33344

In the spectrum of processor architectures there are simple, very fast clock speed Alpha's on one end and architecturally very complex X86 processors on the other end. The first gets throughput via the fast clock speed while the other gets it through more efficient register renaming, branch lookahead, etc. The complex architectures tend to have longer logic paths which slow the cycle time down. This is THE good example of why just looking at clock frequency is a terrible metric to compare processors; it really needs to be done by measuring throughput via benchmarking. Now, if we enlightened can convince Joe and Jane Sixpack........ Frank