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To: Donald B. Fuller who wrote (3102)7/9/1998 12:38:00 AM
From: SemiBull  Read Replies (2) | Respond to of 3736
 
SpeedFam Announces Second Major Korean CMP Customer

Receives Order for First Auriga-C Apex CMP System

CHANDLER, Ariz.--(BUSINESS WIRE)--July 8, 1998--SpeedFam International, Inc.(NASDAQ:SFAM - news), a leading supplier of high-throughput chemical mechanical planarization (CMP) systems for the semiconductor industry, as well as flat surfacing processing systems for the thin film memory disk media and silicon wafer industries worldwide, today announced that it has received an order from its second major semiconductor customer in Korea for its new Auriga-C Apex CMP system. The newly introduced Auriga-C Apex CMP system will be used for 64M DRAM oxide applications and is expected to ship during the first quarter of fiscal 1999.

''We continue to make positive in-roads in capturing one of the critical semiconductor manufacturing markets in the Far East,'' said Makoto Kouzuma, president and chief executive officer for SpeedFam
International. ''With the recent introduction of the HF post-cleaning enhancement module for the Auriga-C, we continue to meet our customers' needs for optimal productivity and lowest cost-of-ownership compared to other competitive configurations.''

The Auriga-C Apex features a hydrofluoric acid (HF) cleaning module to enhance the performance of the Auriga-C's integrated post-CMP cleaning system. The application of diluted HF etches the surface of the polished semiconductor device layer to improve the surface condition and to reduce metallic ion contamination levels present after polishing, thus decreasing overall defect levels for improved device
yields. The single wafer process method utilized in the Auriga-C Apex provides precise, consistent process control for applying wet cleaning technology and reduces the CMP cost of ownership by integrating this technology into a high throughput, integrated CMP system.

Other Auriga customers added to SpeedFam's worldwide customer list during the past fiscal year include White Oak Semiconductor, a joint venture between Motorola Semiconductor Products Sector and Siemens Semiconductor Group, Silicon Manufacturing Partners PTE, Ltd., a joint venture between Lucent Technologies and Chartered Semiconductor in Singapore, Holtek Microelectronics in Taiwan, Samsung in Korea, and Matsushita Semiconductor Corporation of America (MASCA).



To: Donald B. Fuller who wrote (3102)7/9/1998 7:04:00 PM
From: Grand Poobah  Respond to of 3736
 
I'm not a semi engineer but believe there is no special difference in the CMP requirement between .25, .18, .13, etc.. They are just planarizing the wafers, not etching them.

You are right, there's no difference in CMP requirements based on the geometry of the process, per se. The flatness produced by CMP is better than needed for the tighter depth-of-focus requirements of the smaller linewidths for the foreseeable future. However, the shrinking geometries bring along with them other changes in the processes that do affect CMP. These are generally in the form of new materials for CMP to polish. For example, around 0.6 or 0.5-um, tungsten plugs became widely used, and CMP had to polish tungsten. Around 0.35 or 0.25-um, shallow-trench isolation replaced LOCOS, and CMP had to polish the substrate with few enough defects to lay down a good gate oxide. At 0.18 or 0.13-um, copper interconnects and low-k dielectrics are going to give CMP new materials to polish. So it is not really the smaller geometries themselves that are driving CMP advances, but the new process steps and materials.

G.P.