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Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: NightOwl who wrote (5614)	7/12/1998 7:11:00 AM
From: Ibexx	Respond to of 93625

Thread, Money flow index of RMBS increased significantly during the last 2 weeks--almost at previous high (when the stock was traded at $70-80s) Ibexx

To: NightOwl who wrote (5614)	7/12/1998 10:39:00 AM
From: Guy E. Fleming	Respond to of 93625

Dear NightOwl: Lurk less and write more! Your message was very useful and well-written. Thanks! Guy E. Fleming

To: NightOwl who wrote (5614)	7/12/1998 1:02:00 PM
From: Alan Bell	Read Replies (1) \| Respond to of 93625

Nightowl, I find the key advantage for Rambus technology to be something other than what is described in the articles. They have changed the boundary to interface to the memory. Previously it had been the signals external to the Ram chip. Rambus changed this to signals internal to the Asic on the verilog core they provide. In other words, a designer building an Asic interfaces to well defined signals inside the Asic by means of the chip logic description language - verilog or VHDL. By making this change, Rambus is responsible for (but has complete control over) the path from the Asic pads into the Ram chip. So this path becomes an integral unit and can be engineered by people with the appropriate talents (including analog, standing wave signals, etc). No longer does this engineering have to be repeated by each group building a system. As speeds increase, this kind of integral design approach becomes essential. Interfacing at the chip boundary will not be sufficient. It also allows the signals and protocols connecting their core with the Ram to be far more complex. Only Rambus needs to know the details of the bus protocol. It doesn't need to be explainable to the engineers using the chips - they design to the asic core interface. Perhaps in the future, that protocol could be expanded to incorporate a processor's speculative execution. Latency L1 and L2 cache's are the main attack in processors on latency. Right now, pin count issues have precluded hooking directly to the processor. But with Rambus's reduced pin count, it is conceivable that memory could be attached directly to the processor (in addition to the memory on the chipset.) This would reduce latency because then the memory access would avoid the delay in the chipset. -- Alan