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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Maxwell who wrote (35130)	7/26/1998 11:01:00 PM
From: Elmer	Respond to of 1572611

Re: "You have a PhD and go to many conferences and symposiums. I on the other hand never go to those geek fests. Yet I understand and know more than you. (Refering to Yousef)" Not from my point of view. EP

To: Maxwell who wrote (35130)	7/26/1998 11:20:00 PM
From: Yousef	Read Replies (2) \| Respond to of 1572611

Maxwell, Re: "Do you know why I like to reply your posts so much? The reason is that you are supposed to know more process technology than me." AND I do know more than you, Maxwell ... I see you have another "take home" test from Bert's SOF. I want to see you get good grades, so I will help you once again. Re: "1) Copper process reduces backend process by 40%." This is wrong, Maxwell ... Let me go through the process step comparisons. I will start at dielectric deposition for each process: Standard Al Process .................... Copper Damascene Process 1)Dep Dielectric HDP Oxide ............. 1)Dep Dielectic (SiO2/Si3N4/SiO2) 2)Polish Dielectric ............................2)Contact Lithography 3)Contact Lithography ......................3)Etch Contacts & Strip Resist 4)Etch Contacts & Strip Resist ..........4)Trench (Cu) Mask 5)Dep Seed Layer IMP Ti/TiN ...........5)Etch Trench (Oxide) & Strip Resist 6)Dep Tungsten ...............................6)Dep Seed Layer IMP Ta or TiN 7)Polish Tungsten ............................7)Dep/Electroplate Copper 8)Dep Aluminum (Ti/AlCu/TiN)..........8)Polish Copper 9)Aluminum Lithography 10) Aluminum Etch & Resist Strip So you can see, Maxwell ... 20% fewer steps. Re: "2) Copper conductivity is about 50% better than Al ... ...Ohm Law:...Power=RII ...Lower power means lower power dissipation" Well Maxwell, at least you got Ohm's Law correct ... I can't believe that you think that Aluminum interconnect plays a large role in chip power dissipation. People on this thread will "laugh" at you ... the FET's are what dissipate power on the chip NOT metal interconnect. Even Bert will give you an "F" on that one. Re: "3) Low K is a breeze to integrate to copper to lower capacitance. ...Fluorinated HDP (K~2.5-3) is cakewalk with Cu damascene." This statement is NOT true ... Fluorinated HDP will not give K values below 3. To achieve this, you need Spin-On-Glass (SOG) will more exotic materials that are difficult to integrate with Copper Damascene. Did you notice that Silicon Nitride layer in the Cu flow used as an etch stop in the dielectric "sandwich" ?? ... this silicon nitride is needed to maintain control of the trench (Cu) thickness. Please see my last post to you for clarification: Message 5232529 This silicon nitride layer considerably raises the "effective K" for the Copper Damascene dielectric ... in fact you need Low K just to get back to the Aluminum case. Re: "AMD will ENJOY YEARS of LOW COST MANUFACTURING CPUs while Intel engineers battle it out when to attack the COPPER MONSTER." Just more Copper HYPE, Maxwell ... You must have a "Phd" in that field. <ggg> Make It So, Yousef

To: Maxwell who wrote (35130)	7/26/1998 11:40:00 PM
From: Paul Engel	Read Replies (1) \| Respond to of 1572611

Maxwell - Re: Yousef & "Yet I understand and know more than you. Your posts have demonstrated a lack of understand in the technology. " Yousef knows an incredible amount regarding wafer processing. Although you seem knowledgeable, you make blanket, naive statements such as: {======================} "Copper conductivity is about 50% better than Al. ...Ohm Law:...Power=RII ...Lower power means lower power dissipation ...Power=CfV^2 for a CPU. Lower power means you can go to higher frequency without burning the CPU and can be put in notebooks. ...Lower resistance means you can scale the die size down further since the metal trace resistance is now 50% less." {=======================} This totally ignores the implementation problems with copper - especially in a damascene type of process. The BARRIER FILMS required to encapsulate the copper - to prevent diffusion into the oxides and bulk silicon - CONSUME SIGNIFICANT AMOUNTS OF SPACE/VOLUME that should go to copper. The net result is to REDUCE the cross section of copper interconnects - since the barrier materials take up the rest - which NEGATES THE resistivity improvements. Remember :R = (rho*l)/A, where A is the cross sectional area of conductor of length l and resistivity, rho. The resultant smaller A - with barrier films surrounding the copper [with a fixed trench size dictated by the metal pitch], counters the effect of the reduced rho for damascene copper with barrier films. Also Re: "..Fluorinated HDP (K~2.5-3) is cakewalk with Cu damascene. ...AMD will have both Low R and Low K" If this is such a "cakewalk" for AMD - why hasn't AMD implemented it - and why did they have to go to Motorola for the copper process? Face it - AMD has no cakewalk at all in wafer processing. Paul

To: Maxwell who wrote (35130)	7/27/1998 12:11:00 AM
From: zaq	Respond to of 1572611

I only wish AMD could also make money along with this technology enjoyment!! -zaq

To: Maxwell who wrote (35130)	7/27/1998 12:12:00 AM
From: Time Traveler	Respond to of 1572611

Maxwell, Have you read "Computing with DNA" in this month's issue of Scientific American? I think AMD should also seek help in quantum computing and DNA computing besides copper. What do you think? Time Traveler