Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Yousef who wrote (35134)	7/28/1998 12:37:00 AM
From: Petz	Read Replies (1) \| Respond to of 1572570

so you see, Maxwell, "only" 20% few steps for copper. Yeah, and most probably, 20% fewer LAYERS (4 vs. 5) Petz

To: Yousef who wrote (35134)	7/29/1998 12:47:00 AM
From: Maxwell	Read Replies (2) \| Respond to of 1572570

Yousef: Heh, your post is much better this time but you are still wrong. Have you heard of Dual Damascene? Well it goes as followed: Standard Al Process .................... Copper Damascene Process 1)Dep Dielectric HDP Oxide ............. 1)Dep Dielectic 2)Polish Dielectric .....................2)Contact/Trench Lithography 3)Contact Lithography ...................3)Etch Contacts & Strip 4)Etch Contacts & Strip Resist ..........4)Dep Seed Layer 5)Dep Seed Layer IMP Ti/TiN .............5)Dep/Electroplate Copper 6)Dep Tungsten ..........................6)Polish Copper 7)Polish Tungsten ..................... 8)Dep Aluminum (Ti/AlCu/TiN)........... 9)Aluminum Lithography................. 10) Aluminum Etch & Resist Strip....... If my calculation is right that comes out to be 40%! If you don't know what Dual Damascene ask your Intel boss to send you to the next symposium on copper process. Also I also want to let you know that Cu plating is a BATCH PROCESS whereas Aluminum dep PVD is a single wafer process. The throughput of Cu plating is unbelievable. This will improve my 40% advantage SIGNIFICANTLY. <<Well Maxwell, at least you got Ohm's Law correct ... I can't believe that you think that Aluminum interconnect plays a large role in chip power dissipation. People on this thread will "laugh" at you ... the FET's are what dissipate power on the chip NOT metal interconnect.>>> Do I have to explain everything to you? With using copper I can make smaller metal lines with same resistance as Al. Smaller metal lines means I can shrink my die. Smaller die means I can make my FET smaller with smaller Leff. Smaller transistor means lower power dissipation. I also want to add that my dual damascene process has very low contact resistance compared to tungsten vias. This will reduce my power dissipation as well since I don't have to put such a high voltage to get high current out. As for low K, SOG such as flowable oxide is easier to manufacture than fluorinated HDP with K in the mid 2. The difference between 2.5 and 3 is insignificant compared to k=4 for SiO2. Anyway so much talking to you. Your company will go to copper eventually and you will see that I am right. Maxwell