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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Maxwell who wrote (35178)	7/29/1998 2:12:00 AM
From: Petz	Read Replies (4) \| Respond to of 1572594

3 Cheers for Maxwell, he's finally shut up Yousef! EOM Yousef's 0 knowledge of Dual Damascene process means that inquirers here should ignore his comments on Cu technology. Yousef: Heh, your post is much better this time but you are still wrong. Have you heard of Dual Damascene? Well it goes as followed: Standard Al Process .................... Copper Damascene Process 1)Dep Dielectric HDP Oxide ............. 1)Dep Dielectic 2)Polish Dielectric .....................2)Contact/Trench Lithography 3)Contact Lithography ...................3)Etch Contacts & Strip 4)Etch Contacts & Strip Resist ..........4)Dep Seed Layer 5)Dep Seed Layer IMP Ti/TiN .............5)Dep/Electroplate Copper 6)Dep Tungsten ..........................6)Polish Copper 7)Polish Tungsten ..................... 8)Dep Aluminum (Ti/AlCu/TiN)........... 9)Aluminum Lithography................. 10) Aluminum Etch & Resist Strip....... If my calculation is right that comes out to be 40%! If you don't know what Dual Damascene ask your Intel boss to send you to the next symposium on copper process. Also I also want to let you know that Cu plating is a BATCH PROCESS whereas Aluminum dep PVD is a single wafer process. The throughput of Cu plating is unbelievable. This will improve my 40% advantage SIGNIFICANTLY. <<Well Maxwell, at least you got Ohm's Law correct ... I can't believe that you think that Aluminum interconnect plays a large role in chip power dissipation. People on this thread will "laugh" at you ... the FET's are what dissipate power on the chip NOT metal interconnect.>>> Do I have to explain everything to you? With using copper I can make smaller metal lines with same resistance as Al. Smaller metal lines means I can shrink my die. Smaller die means I can make my FET smaller with smaller Leff. Smaller transistor means lower power dissipation. I also want to add that my dual damascene process has very low contact resistance compared to tungsten vias. This will reduce my power dissipation as well since I don't have to put such a high voltage to get high current out. Petz (repeating most of Maxwell's authoritative post)

To: Maxwell who wrote (35178)	7/29/1998 10:02:00 AM
From: Yousef	Read Replies (3) \| Respond to of 1572594

Maxwell, Re: " Have you heard of Dual Damascene? Well it goes as followed:" I am very disappointed in your technical understanding ... the process flow that I originally gave you was for a dual Cu damascene process flow. Your flow won't work ... want to explain how you do contact masking and trench masking at the same time as well as the etch ... didn't think so. Re: "Smaller die means I can make my FET smaller with smaller Leff. Smaller transistor means lower power dissipation." Actually Maxwell, smaller Leff will mean more drive current (Idsat) which will increase the power of that small FET. The way to reduce power is to lower the operating voltage ... funny, you didn't mention that. Re: "As for low K, SOG such as flowable oxide ..." I believe in your original post, you were talking about Fluorinated HDP, not SOG films ... trying to change the subject material, Maxwell. <ggg> Re: "Anyway so much talking to you. Your company will go to copper eventually and you will see that I am right." Maxwell, I don't think I ever said that Intel would never go to Copper ... just not for the .18um generation. Beyond that, I expect that Intel will use Copper in their .13um process. In closing Maxwell, your post was very poor on technical details and you obviously don't know nearly as much as you claim. Make It So, Yousef