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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Yousef who wrote (35190)	7/29/1998 12:37:00 PM
From: MikeyB	Read Replies (1) \| Respond to of 1572512

I am curious. What makes everybody assume that AMD has not been doing process development on low-K dielectrics such as SOG and flourinated HDP??? And what would prohibit them from implementing a low-K process along with Cu?? It also seems that everyone agrees that a Dual Damascene approach has fewer process steps. Whether the difference is 20%, 40% or 60%, the difference is still significant. It also appears that everybody thinks that each process step requires the same cycle time. The cycle times of each step vary considerably. Using Yousef's process flow (which is the correct one), I suspect that his 20% reduction of process steps would result in approximately a 40% decrease in cycle time. MikeyB PS: To all the experts out there, what are the benefits of indium implants?

To: Yousef who wrote (35190)	7/29/1998 6:52:00 PM
From: Maxwell	Read Replies (2) \| Respond to of 1572512

Yousef: <<I am very disappointed in your technical understanding ... the process flow that I originally gave you was for a dual Cu damascene process flow. Your flow won't work ... want to explain how you do contact masking and trench masking at the same time as well as the etch ... didn't think so. >>> The process flow I gave you is the ADVANCED DUAL DAMASCENE process. If you are nice to everyone here I will give you the secret to this process. It is a patented technology. Maxwell

To: Yousef who wrote (35190)	7/30/1998 12:35:00 AM
From: Maxwell	Read Replies (2) \| Respond to of 1572512

Yousef: ______________________________________________________________________ Advanced Dual Damascene: 1) Photo Step: a) You spin on 2 types of resists, say resist 1 (R1) on bottom and resist 2 (R2) on top. There is a developer 1 (D1) that only develops exposed R1 but not R2 and developer (D2) that only develops R2 but not R1. b) You expose the contacts first then develop R2 first by dipping into D2 then develop R1 by dipping into D1. What you have then are your contacts fully developed. c) You then take the same wafer and expose the trenches. Then develop into D2. Thus the bottom of your trenches will just be exposed R1 undeveloped. The contacts will be clean without any resists and just have SiO2 on the bottom. Afterward you go to etch 2) Etch Step: Etch is a complicated in-situ process a) You first etch the SiO2. This etch process must have good selectivity to exposed R1. In this step, you only etch the contact and the trench are masked by exposed R1. This is a time etch process. b) When the time is finished you then in-situ change the gas to etch the exposed R1. This must also have good selectivity to SiO2 or to whatever dielectric you use. This can be an end-point process. Once the end point is finished then you change your gas back to etch your SiO2 in the trenches and contacts. By the time you finish the trenches and contacts have been formed to your desire. 3) Barrier metal dep./ Cu electroplate 4) Polish 5) Oxide Dep 6) Repeat step 1-5 to go to the next metal layer. ______________________________________________________________________ BTW: As pointed out by someone earlier that in Aluminum process there are 2 polishing steps, oxide polishing and tungsten polishing. In the copper dual damascene process there is only 1 polish step. I hope you know that polishing is a very expensive process. You see Yousef I am not kidding you when I talk about advanced dual damascene process. I just saved your company $2K to send you to the next symposium on advanced dual damascene process. So far I have kept my record clean and you lose. Maxwell