Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : CYRIX / NSM -- Ignore unavailable to you. Want to Upgrade?

To: Steve Porter who wrote (28556)	7/28/1998 6:01:00 PM
From: Scumbria	Read Replies (4) \| Respond to of 33344

An intelligent CPU might dedicate an extra step on the front end of the CPU (i.e. instruction decoder) to get the data from memory and into the cache before the instruction starts executing. Steve, I'm glad to see the thread still has a pulse. In order to retrieve data from memory, the processor has to generate a physical address. It is not possible in the x86 architecture to generate that address without beginning execution of the instruction. Power PC provides "touch" instructions allowing software to bring data into the cache early. Merced is rumored to have some more sophisticated techniques for accomplishing the same thing. Scumbria