Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : CYRIX / NSM -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (28558)	7/28/1998 6:44:00 PM
From: Joe NYC	Respond to of 33344

Scumbria, I'm glad to see the thread still has a pulse. I am holding my breath waiting for the chips from South Portland. I am getting a little light headed, but the pulse is still there. Joe

To: Scumbria who wrote (28558)	7/28/1998 6:45:00 PM
From: FJB	Read Replies (1) \| Respond to of 33344

"The clear message to Intel salespeople is: 'Celeron the world,'" said a source briefed on the schedule. "They're telling their people, 'If you don't sell Celeron, you don't have a job.'" The company last week moved a planned Sept. 13 launch of two new Celerons with cache, the 333MHz and the 300MHz, to Aug. 24, when a massive retail campaign is planned, sources said. In addition, the company plans to take a deeper price cut on Oct. 25 than originally planned. The 333MHz with 128K cache will drop to $155 on that date, compared with a previously planned $177. The 300MHz with 128K cache will drop to $92 on Oct. 25, down from a previous $135. The efforts appear aimed at quickly putting behind Intel the poor reception of its cacheless Celerons. Tim Christensen, a buyer for Missoula, Mont.-based Vann's, said Celeron systems were moving-barely. "Celeron isn't a bomb, but it isn't really selling," he said. 207.240.177.145

To: Scumbria who wrote (28558)	7/28/1998 8:03:00 PM
From: Steve Porter	Read Replies (3) \| Respond to of 33344

Scumbria, What is wrong with the following scenario happening: Add a "pre-decode" unit which peeks into the instructions and scans for those which will need data not in the cache and go and get it. Sure it adds more silicon, but 90% of the work would be duplication and minor modifactions of the current decode units. I mean let's face it, when people start talking about creating huge L2 caches on the die, it is hardly too much silicon to ask for a partial decode unit, especially when it would DRAMATICALLY improve performance. Just think, if you could have a 2-3 clock cycle head start on fetching data from RAM! Steve

To: Scumbria who wrote (28558)	7/29/1998 1:22:00 AM
From: Paul Engel	Read Replies (1) \| Respond to of 33344

Scumbria - Re: " It is not possible in the x86 architecture to generate that address without beginning execution of the instruction. " Correction. The original 8086 had a 6 byte instruction pre-fetch queue. The BUS INTERFACE UNIT generates the addresses and loads up to 6 bytes into the queue IN ADVANCE (there were no caches back in those days) - and the execution unit could load instructions from the queue. The 8088 had only a 4 byte instruction pre-fetch queue. Paul