To: Tony Viola who wrote (35441 ) 8/3/1998 9:36:00 PM From: Adrian Wu Read Replies (2) | Respond to
Tony: The K7 will not be just a single chip design but has a tremendous amount of flexibility. Like the Alpha, it can incorporate an L2 cache on a backside bus at half-speed or full speed. In that configuration, it makes use of the cache on the motherboard as an L3. To lower cost, it can omit the L2 from the chip packaging entirely and make use of the cache on the MB as an L2. Most of the cost of the PII is associated with the L2 cache, hence the Celeron. This will not be problem with the K7. The problem with the P6 bus protocol is that it cannot support an L2 cache on the "frontside" bus. The K7 is designed to eventually succeed the K6 as a mainstream processor, much like the PII replaced the Pentium. It should not be any more expensive to manufacture than the Celeron. AMD can also produce a variety with different size and speed of the L2 on the backside bus to satisfy customer needs. This design can also migrate to copper interconnect technologies by the year 2000, enabling them to achieve speeds of 1GHz. Initial K7s will be 0.25 micron, migrating rapidly to 0.18.
