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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Elmer who wrote (35477)	8/4/1998 5:38:00 AM
From: Adrian Wu	Read Replies (1) \| Respond to of 1574028

"I see nothing whatsoever about the P6 bus protocol that would disallow L2 cache on the MB, assuming there were no L2 already on the Die/Slot/Package" Why did Intel not include the option of a MB L2 for the 440EX chipset which was designed for the cacheless Celeron? The reason is because the P6 bus protocol was designed to have a separate bus for the L2 cache ("backside bus"), and not designed to accommodate an L2 on the frontside bus. Otherwise, it would make perfect sense for Intel to design the 440EX with an L2 cache option to improve the dismal performance of the Celeron. Adrian