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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Tenchusatsu who wrote (36708)	9/3/1998 2:44:00 AM
From: Jim McMannis	Respond to of 1571146

Ten, RE:"But of course, if you listened to Jim's words, "People don't care about performance; they care about MHz!" (quote taken severely out of context.)" I believe I qualified that by saying "average consumer"... As in walking into a Best Buy and figuring out what computer to buy. PR rating could be substituted but it can be confusing. The ability of Intel to stay ahead in the Mhz game hasn't hurt their bottom line. Jim

To: Tenchusatsu who wrote (36708)	9/3/1998 12:05:00 PM
From: Paul Engel	Read Replies (1) \| Respond to of 1571146

Tenchusatsu - Re: "the first silicon of Mendocino was so clean that Intel is using it to begin volume shipments." Now where have I heard that before ? As for Sharptooth, Intel has had fully functional Dixon Silicon (256 KByte L2 on-CPU cache - same as Sharptooth) for over a nonth now. Intel was leaning to make this a Mobile Pentium II chip - to simplify the MMO modules - by eliminating the external L2 cache - and heat! When AMD ships their Sharptooth (Next Year), they will have a bevy of competitive products from Intel to sell against. Intel's Katmai will be the leader, and Coppermine - a 0.18 Micron Katmai - won't be too far behind. Paul

To: Tenchusatsu who wrote (36708)	9/3/1998 2:06:00 PM
From: Ali Chen	Read Replies (2) \| Respond to of 1571146

<"whirlwind development effort" of Mendocino, "Originally expected to ship late this year, the product was pulled into an August release. Although most processors take two or three tries before they can be shipped, the first silicon of Mendocino was so clean that Intel is using it to begin volume shipments." Wow. Tenchusatsu> ---------- You must be too over-exited, men. The P-ii core already has a debugged (fully? Xeon?) controller for the backside L2 cache, with all IO pads on the proper side. Any EE student can glue a SRAM to this chip flawlessly. It would be a total shame if Intel had to spin another silicon in such a sky-rocket upgrade. <BECAUSE THE EXTERNAL L2 CACHE IS DEADLOCKED at a FIXED 100 MHz ! Good point. Very good point. > Wrong point.